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Based on DDS technology to generate a linear FM signal

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1 DDS (direct digital frequency synthesizer) the basic principles of

Direct Digital Synthesis is a departure from the concept phase direct synthesis of a required frequency waveform synthesis. DDS to the form of a series of digital signal through the Digital to analog (DAC) to convert the form of analog signals, and its basic structure as shown in Figure 1.

Based on DDS technology to generate a linear FM signal

DDS by the phase accumulator, adder, waveform memory (ROM), digital multipliers, D / A converters and low-pass filter (LPF) component. DDS is the core of the phase accumulator, a phase adder and a register (REG) constitute a cascade. Reference clock fc in the control, the phase accumulator for frequency control word K linear accumulation, output and phase control with P add the word as address, for addressing of the ROM. Stored in ROM is a sampling, a quantitative treatment of a cycle of periodic continuous wave signal the range of values, that is, the phase with a sampling cycle corresponding to the wave function look-up table, the address corresponds to a different phase of this cycle signal value of the different coding rate. ROM range of output values to be encoded digital amplitude control multiplier word A-weighted, weighted by the magnitude of the value of coding D / A converter into a corresponding wave of the ladder, and then smoothed by the low-pass filter can be synthesized after the signal analog waveform. Synthesis depends on the signal wave stored in ROM data rate value, so can generate arbitrary waveform DDS.

Phase accumulator word length set to N, the DDS output frequency and frequency fo-resolution (that is, the minimum output frequency) △ fmin are as follows:

Based on DDS technology to generate a linear FM signal

As long as N is large enough, DDS can be very small frequency resolution. To change the DDS output frequency, as long as the change in frequency control word K can.

It is worth noting that, according to Nyquist sampling theorem, for continuous signals in a sampling cycle, the sampling frequency can not be changed, so the use of DDS signal synthesis, the synthesis of a signal cycle, the frequency control word K is not changed, K is changed each time should be continued until at least 2N / K a DDS clock cycles, that is, 2N/K/fc.

By changing the phase control word P can control the output signal of the phase parameters, set up phase of the word length adder for the M, when the phase control word changing from 0 to P (P ≠ 0) when, ROM input to the output of the phase accumulator and phase control, and the P word, so the magnitude of the output phase will increase the value of 2πP/2M, so that the final output of the analog signal generated phase shift.

DDS output signal amplitude can be after the ROM to the realization of a digital multiplier, ranging from control of the ROM word A play by the magnitude of the output value of the role of the weighted code.

It can be seen, when the DDS phase accumulator word length and phase adder word length is determined by changing the K, P, A can effectively control the DDS output frequency of the analog signal, the phase of rent increase, which is DDS technology modulation characteristics.

2 VHDL language of DDS

For simplicity, the following describes only the set of DDS frequency control word K, phase control and amplitude control word P word A not be taken into account, the deal could be on and so forth. DDS output sine wave signals for.

As the sine wave odd symmetry on the π on π / 2 and 3π / 2 dual-symmetric, so waveform memory (ROM) in the only store of its 1 / 4 cycle of the range of value coding. Specifically, ROM to store sine 0 ~ π / 2 phase 256 within the scope of the range of values of sampling points, using 8-bit encoding. The DDS output is 9, the highest place as a symbol to distinguish between positive and negative range of values, "0" that is, "1" means negative. ROM address for the 8-bit addressing, and the use of the phase accumulator word length of 10. To distinguish the highest sine wave before and after the half-cycle, "0" for the first half of the cycle, ranging from the value of a positive, "1" for the latter half of the cycle, ranging from a negative value. Times to distinguish between high sine wave before and after the half-cycle before and after the 1 / 4 cycle, "0" for the former 1 / 4 cycle phase accumulator address is addressing the low-8, "1" for the post-1 / 4 cycle, addressing address low 8-bit phase accumulator of the counter-check.

DDS using VHDL to achieve the core of the source as follows:

Based on DDS technology to generate a linear FM signal

Based on DDS technology to generate a linear FM signal

Xilinx ISE 8.2i in the development environment for their simulation results, as shown in Figure 2.

Based on DDS technology to generate a linear FM signal

Sweep signal the emergence of 3

The use of the modulation characteristics of DDS technology can easily have swept signal, only the control of the DDS frequency control word K, its design with the expected changes to the law.

In order to achieve the use of DDS Sweep Sweep signal bandwidth of the scope of the various frequency fi, is necessary to determine the appropriate frequency control word Ki, which is easy to calculate Ki values of a series of requirements. With the basic principles of DDS is similar to the design requirements would be in line with a series of Ki values stored in a look-up table in the. Reuse of a counter cycle count, the output will be addressing as a look-up table address, this constant cycle of reading the various look-up table in the Ki. This allows control by the Ki of the DDS output is always expected in the design of the various changes in the frequency fi, to sweep the purpose. Among them, the cycle time counter is to be achieved by the sweep of the Sweep Signal cycles of counting and the scope of counter sweep signal with swept frequency bandwidth within the scope of the corresponding number of points.

These are the use of DDS to achieve the basic ideas swept signal, the following ideas to achieve this the main part of VHDL source code:

Based on DDS technology to generate a linear FM signal

Xilinx ISE 8.2i in the development environment for their simulation results as shown in Figure 3.

Based on DDS technology to generate a linear FM signal

4 Conclusion

VHDL is the IEEE's industry standard hardware description language, can describe the function of the hardware circuit, the signal connections and regular relations, used to describe the field of electronic engineering, validation and design of electronic circuits has been widely accepted and applications. The use of DDS technology have a variety of modulation characteristics of the modulation signal is simple and convenient, easy to implement. It is easy to see from the text, the VHDL language and the design of DDS technology to generate up FM signals, visual fast, highly operable, will be more widely used.

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