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CMOS low-power low-noise amplifier design and optimization

Print View , by: iSee ,Total views: 8 ,Word Count: 2144 ,Date: Thu, 7 May 2009 Time: 5:55 PM

As wireless communication technology rapid development of the miniaturization of wireless terminals, low power, low-cost, high-performance Radio Frequency integrated circuits has become (RFIC) the inevitable trend of development. MOS tube past the relatively poor high-frequency performance, the traditional rf transceiver mainly GaAs, BiCMOS, Bipolar technology to achieve, but very expensive and does not help with the digital baseband part of CMOS monolithic integration [1]. In recent years, with sub-micron, deep sub-micron CMOS technology matures, cut-off frequency fT rising, CMOS technology has been in terms of performance to meet the needs of RF, and CMOS technology with low cost, high integration, power consumption and small characteristics of CMOS RFIC therefore has become a hot spot on the R & D [2].

In the receiver design, to get a good overall system performance, superior performance lies in the front-end, low-noise amplifier (LNA) is one of the most critical circuits. LNA is the first class to receive the circuit directly in the face of an antenna to receive all kinds of noise contained in weak signal, the characteristics of the whole system have a direct impact on noise performance. LNA requires a good noise figure, and to provide sufficient gain to ensure that the whole system has the smallest receiver NF; At the same time when the received signal is larger, should be sufficient to reduce the linearity of signal distortion. Modern mobile communication devices to enable low-power LNA design is becoming increasingly important, the literature [3] proposed PCSNIM technology is the best low-power narrow-band LNA design optimization technology, in low-power constraints, while the noise performance, input matching is optimized, but also PCSNIM technical deficiencies. This article considers the gain, noise, power consumption, linearity, matching and other indicators of the impact of the entire transceiver system to further improve the LNA circuit structure, in order to get the best system performance.

In this paper, the literature [1-5] in research as a starting point for improving SNIM and PCSNIM using SMIC RF 0.13μm technology, the realization of the IEEE802.11a WLAN used monolithically integrated LNA. Simulation data show that the LNA power consumption of only 3mW, gain of 14.3dB, noise figure of about 2.2dB, IIP3 than-3.6dBm, S11 is about-23dB. Simulation through the design and testing of comparison, to verify the correctness of the theoretical analysis. Method of low-power LNA designs have a certain significance.

1 low-power LNA design method

1.1 SNIM analysis of the structure of LNA

Figure 1 is easy to achieve input impedance matching, from the signal source to see the input impedance Zin of the network as follows:

CMOS low-power low-noise amplifier design and optimization

CMOS low-power low-noise amplifier design and optimization

One Lg, Ls for planar spiral inductors on-chip, M1 is the total of the source of amplification tube, tube cascode isolation from the role of M2, M1 gate leakage reduction of the Miller effect capacitance. Style (1) show that when:

CMOS low-power low-noise amplifier design and optimization

, The input matching network input impedance for the resonator so pure resistance, then as long as the guarantee:

CMOS low-power low-noise amplifier design and optimization

Can be in the frequency? Brown 0:00 input impedance matching.

By the two-port noise theory of knowledge [2], two-port matching network in the noise, you can achieve the minimum noise figure Fmin as follows:

CMOS low-power low-noise amplifier design and optimization

In which γ, δ, c in the long trench devices were 2 / 3, 4 / 3, 0.395j, is a constant related with the process. Impedance matching requirements of the noise source impedance ZS equivalent to the best noise Zopt. When the two are not equal, the actual noise figure is:

CMOS low-power low-noise amplifier design and optimization

Which CMOS low-power low-noise amplifier design and optimization . From the equivalent noise resistance Rn of expression, it is not the increase in the effects of capacitance and inductance only depends on the value of gm, so large size and high power transistors lead to smaller Rn.

References [1], [3] for detailed Zopt derived optimization process, the results are as follows:

CMOS low-power low-noise amplifier design and optimization

SNIM circuit is not optimized for best noise source impedance are much greater than the impedance, it can use the type (6), (7) of Cgs is inversely proportional to Zopt with the characteristics of M1 increased to increase the size of pipe Cgs, reduced Zopt, the ultimate realization of the noise matching circuit. And increasing the size of M1 means to increase the power consumption (in order to ensure that M1, M2 are in saturation voltage and a certain margin, M1 tube gate-source voltage can be very small changes in the scope). Therefore, the use of the LNA design SNIM have considerable power, this does not meet the requirements of low-power circuits.

1.2 PCSNIM analysis of the structure of LNA

Derived in accordance with the above analysis does not change in the size of M1 control conditions, in the M1 Tube gate-source capacitance C1 in parallel to the indirect increase gate-source capacitance (Figure 2), the realization of power-constrained noise and input matching [3] .

CMOS low-power low-noise amplifier design and optimization

From the signal source to see the input impedance of the network as follows:

CMOS low-power low-noise amplifier design and optimization

Input matching network (quality factor for the Qin) in the resonator, the gate-source voltage is the input voltage times the Qin. System for the equivalent transconductance Gm [1] [4], can be seen parallel equivalent capacitance Cgs system reduces transconductance.

CMOS low-power low-noise amplifier design and optimization

Knowledge derived from the above: the introduction of capacitive feedback negative feedback will source inductor Ls increases, inductance Ls resulted in increased system gain and noise performance dropped to some extent, the deterioration; capacitance feedback will enable the system to introduce the equivalent inter - Introduction to reduce, resulting in reduced system gain 20logk; allowing the system to reduce the cut-off frequency for the original 1 / k, to some extent, the deterioration of the noise performance of the system.

To sum up, although the use of technology PCSNIM power constrained input match and noise optimization, but the price is also great, especially in the low-power requirements and reduce system gain under the high-frequency characteristics of the deterioration of the system [ 1].

2 IPCSNIM analysis of the structure of LNA

By the above analysis can be seen: the key contradiction is that the introduction of parallel capacitor C1 while the realization of the power-constrained input match and noise optimization, but also lead to system gain and high-frequency characteristics of the deterioration of decline. Ls main effect and the role of input impedance matching, the noise characteristics of the system has little effect. Therefore, capacitor C1 can change the position parallel to an effective solution to this conflict.

To improve the program as shown in Figure 3. In which R1, M3 for the M1 to provide DC operating point, R2 isolate R1 and M3 to the M1 of the impact of noise, R2 the better the general order of magnitude for the megohm; capacitor C2 and C1 similar role, to play the best to reduce noise impedance role such as the type (9), type (10).

CMOS low-power low-noise amplifier design and optimization

From the signal source to see the input impedance of the network as follows:

CMOS low-power low-noise amplifier design and optimization

One C2 (about 100fF) and the C1 equivalent PCSNIM.

The main source inductance LS is generated so that the input impedance of 50? Repeat of the real part, to achieve input impedance matching. Ideal inductance theoretically does not affect the system Re [Zopt], such as the type (6), type (9); LS small (0.7nH), for Im [Zopt] impact can be ignored, such as the type (7), type (10). So the best noise to improve the circuit impedance can be used-type (9), type (10) basis.

3 Design examples and simulation results

In the actual chip, the chip resistors in general a lot of errors, about 20%, R1 fluctuations directly affect the system's DC operating point, the system has great influence on overall performance; and R1 is about 1.5kΩ, the use of chip resistors will occupy a larger chip area. To avoid this problem, M4 can be used to replace the MOS resistance R1. This not only saves the chip area, and the resistance R1 can greatly enhance the accuracy.

C2 in Figure 2 very small (only about 100fF), the smaller the actual on-chip capacitance, the greater the error, but the C2 of the fluctuations of the noise impact. C2 in order to avoid fluctuations in the impact on system performance, the M5 MOS alternative resistance R2, the use of M5-ended gate and source parasitic capacitance of the substrate to replace the C2. M5 can do not only play like R2 as the purpose of noise isolation, and can be completely replaced by C2. This greatly saves the chip area, simplify the complexity of the system. The above analysis, Figure 4 gives a complete low-power LNA design.

CMOS low-power low-noise amplifier design and optimization

The following simulation results are in SMIC RF 0.13μm technology, a single integrated architecture, 5.5GHz operating frequency, 1V voltage work completed. The simulation results compared in Figure 5, Figure 6, as shown in Figure 7.

CMOS low-power low-noise amplifier design and optimization

CMOS low-power low-noise amplifier design and optimization

CMOS low-power low-noise amplifier design and optimization

CMOS low-power low-noise amplifier design and optimization

In this paper, the traditional SNIM and PCSNIM structural analysis on the basis of the power-off against Japan SNIM gain smaller PCSNIM shortcomings, a new framework for low-power LNA design. The program in the power consumption, noise and under conditions of considerable PCSNIM full PCSNIM up for the shortcomings of the gain is too small to achieve high power with a considerable gain SNIM. At the same time to achieve optimal characteristics of the input impedance matching and high frequency characteristics. Theoretical analysis and simulation results ADS is in line to achieve the desired design goals.


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