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ARM9-based S3C2410 processor design of the LCD display system

Print View , by: iSee ,Total views: 20 ,Word Count: 1011 ,Date: Tue, 2 Jun 2009 Time: 8:21 AM

Introduction

Samsung S3C2410 is a production of the RISC-based ARM920T microprocessor core, and its frequency up to 203MHz [1], applied to information appliances, PDA, handheld devices, mobile terminals and other areas, this paper introduces the display based on the S3C2410 system hardware circuit and software design method-driven.

TFT-LCD module's timing requirements

The display module is LQ080V3DG01 selected Sharp's TFT-LCD device, the device resolution of 640 × 480, the control timing diagram as shown in Figure 1, the time parameters such as listed in Table 1 [2].

ARM9-based S3C2410 processor design of the LCD display system

ARM9-based S3C2410 processor design of the LCD display system

Hardware circuit design

Display system in the hardware circuit, S3C2410 connection with the LCD module is the key, S3C2410 internal drive comes with an LCD controller, and its interface with the monochrome, grayscale, color STN and TFT Color LCD type is directly connected, However, according to the LCD by connecting the corresponding register of the type of display mode (see section   Q080V3DG01 its typical power supply voltage Vdd for 3.3V/5V, and the LCD data and control signals in high input voltage Vih range of 2.3-5.5V, low-level input voltage Vil in-0.3-0.9V range and can therefore be connected directly with the S3C2410, the circuit shown in Figure 2.

ARM9-based S3C2410 processor design of the LCD display system

System software design

S3C2410 processor includes the LCD controller registers LCDCOM1-LCDCON5. For LQ080V3DG01, the specific settings of these registers are as follows:

(1) LCDCON1 in, CLKVAL the clock parameters, for LQ080V3DG01, check the value of the domain 1. PNRMODE is the display mode parameters, the domain of 3 values that are used in TFT-type modules, BPPMODE data for each pixel the median parameters for LQ080V3DG01 module, the design can be set to 16bpp, so check the value of this domain 12.

(2) LCDCON2 in, VBPD in Table 1 corresponds to the H parameters, the domain value from 32. LINEVAL corresponds to Table 1 of I parameters, check the value of the domain 479, VFPD in Table 1 corresponds to the J parameter, check the value of the domain 9, VSPW corresponds to G in Table 1 parameters, the domain value from 1.

(3) LCDCON3 in, HBPD Table 1 corresponds to the c parameter, the domain value from 47. HOZVAL counterparts in Table 1 without the D parameters, check the value of the domain 639, HFPD in Table 1 corresponds to the E parameter, the domain value from 15.

(4) only need to set up LCDCON4 can HSPW, which corresponds to Table 1 in the B parameters, the domain value from 95.

(5) LCDCON5 in, BPP24BL used to determine the size of memory 24bpp video-ended mode, the domain value from 0, FRM565 decision 16bpp format video input data.

In the design, but also in the hardware platform based on the S3C2410 embedded Linux operating system installed. In order to make the normal LCD display, but also the need in the embedded Linux system development of the LCD driver.

Framebuffer is Linux2.2.xx appear in a kernel driver interface, the corresponding source file in the Linux / drivers / video / directory, with a total device file for the abstract fbcon.c. This interface will be shown for the frame buffer device abstraction, the user can display it as a memory image. When in the use of frame buffer, Linux will be placed in graphics mode graphics [3].

Based on the LCD face of the main register set up by the results of analysis, the author has developed a mechanism based on FrameBuffer driver S3C2410fb. The following is part of the success after debugging the code, the program can display screen is initialized and set the LCD control register values:

/ * s3c2410fb.c * /

static struct s3c2410fb_mach_infoxxx_stn_info_initdata = (

pixclock: 174757, bpp: 16, xres: 640, yres: 480, hsync_len: 96, vsync_len: 2, left_margin: 40, upper_margin: 24, right_margin: 32, lower_margin: 11, sync: 0, cmap_static: 1.

reg: (/ / set the value of LCD control register

Lcdcon1: LCD1_BPP_16T | LCD1_PNR_TFT | LCD1_CLKVAL (1), lcdcon2: LCD2_VBPD (32) | LCD2_VFPD (9) | LCD2_VSPW (1), lcdon3: LCD3_HBPD (47) | LCD3_HFPD (15), lcdcon4: LCD4_HSPW (95) | LCD4_MVAL (13 ), lcdcon5: LCD5_FRM565 | LCD5_INVVLIEN | LCD5_INVVFRAME | LCD5_HW SWP | LCD5_PWREN ,},};

Concluding remarks

Designed in accordance with this article to connect the hardware interface, you can modify the driver S3C2410 and compile the whole system re-write in Flash, so that after the resumption of the original system will be able to correctly display a static splash screen, and clear picture quality stability, can achieve the desired effects, this device can be in the industrial control and automotive communications in areas such as equipment used for display output.


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