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Show the development of LCoS chips

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LCoS (Liquid Crystal on Silicon) as a new type of display, with large-screen, high brightness, high-resolution, low power and many other advantages of LCoS technology with the production of high-resolution light valve method of gradually place flat panel display industry [1]. In this paper, the design for the three color projectors and the highly integrated chip LCoS display, the use of standard metal 0.6μm-four - two-power CMOS process design and production, the spatial resolution of 800 × 600 pixels, is now at home low-volume semiconductor production line silicon success.

1 LCoS display the physical structure and properties of

LCoS display is a reflective optical modulator will not affect the incident light to each pixel of the cross-sectional area, thus greatly improving the aperture ratio [2]. I designed 3-type projection display system uses a color space for blending method, and 3, respectively, LCoS chip used to control RGB trichromatic graphics, and then through the optical system to achieve color space.

I used the standard 0.6μm-n-well - four-metal CMOS process design monochrome LCoS device profile the physical structure as shown in Figure 1. Map the design into light metal layer 3, metal 4, electrode mirrors designed with the aim of making the metal cover 3 and 4 show the overlap of the active part of the matrix, which completely blocked the incident line, reducing the transistor NM0S PN junction on the source of the photo-generated leakage current. This design prevents caused degradation of the image contrast.

Show the <a href=development of LCoS chips" />

In the chip production process of the CMOS manufacturing process used in the leveling techniques, to ensure that the silicon surface is the optical plane. Leveling process makes silicon LCoS pixels within the local changes in smoothness of less than 100A °, between pixels changes in the overall flatness of less than 500A °. This leveling process will enable the silicon light valve optical performance greatly improved [3]. These improvements include the following three aspects: First, the formation of the surface to improve pixel quality metal mirror, the reflective optical enhancement; Second, in the liquid crystal cell in the latter stages of manufacture, improved formation of the surface of liquid crystal alignment, so that liquid crystal the reliability and characteristics of box to get better; Finally, in pixels on a layer of plating dielectric mirror to further improve the performance of the metal reflector.

In order to improve the success rate of design, the use of projection display system products in the mainstream display performance indicators (see table 1). In this way, on the one hand, the structure will not chip circuit complexity, the difficulty of making a significant increase in design, and the transfer of the gaze of the scientific research; On the other hand, if this analog monochrome display can be successfully realized, could be directly related to mainstream product line.

Show the development of LCoS chips

2 shows the chip circuitry

Figure 2 gives the LCoS chip block diagram of the circuit. The whole circuit chips can be divided into scanning drive, drive out data and display pixel matrix. In order to reduce the chip operating frequency, at the same time conducive to the layout of peripheral drive circuit wiring, and drive out the data into exactly the same electrical structure of the upper and lower groups, respectively, even and odd data line drivers.

Show the development of LCoS chips

LCoS chip display addressing point by point, line scan driver chip at the left, which has 600 drive unit, in accordance with the frame clock pulse to trigger VST and scanning VCK1VCK2 clock synchronization control, from the first line followed by the last line of the drive. On the other hand, the following data on the drive from a choice of 400 two-way shift register and a set of component analog transmission gate. Shift register clock signal pulse HST and the pixel clock under the control of HCK1HCK2, from left to right to signal input analog transmission gate 400, to control their analog signals for video on-time. The results for a constant sampling interval of the monochrome video signal, and direct input to the corresponding video signal electrode line, and thus the role of being selected to scan the pixel electrode line.

LCoS chip monochrome video signal electrode-by-field inversion mode, that is, the role of electrodes in the pixel signal level compared with the superstructure on the glass substrate electrode voltage public, each time frame has changed polarity, so the video signal as a cycle change of the AC voltage, which can prevent the electrochemical degradation of liquid crystal materials.

The use of eda technology design 3-chip LCoS

From the previous analysis can be found, LCoS chip can not direct the use of standard cell, semi-custom gate array, such as methods to achieve. In fact, LCoS chip LSI is the physical layout level, the complexity of its design process, a better design strategy is the use of design and EDA design-level combining methods, the basic design process is the use of top-down design. Specifically, the use of full-custom design features with the Cadence EDA design tools, in accordance with the "top-down" rules to the design of the territory of LCoS chips. First determine the function of the chip micro-significant, performance, allowing the chip area and cost, etc.; and then the structural design, the differentiation of the subsystems as simple as possible; then between the various subsystems into a logical relationship between circuit, logic circuit design and circuit simulation; final approach using full-custom integrated map of the entire LCoS chip. Designed layout but also the structure of the territory through the extraction of parasitic parameters of information and information on the structure of the original description, compared to verify the consistency between them.

3.1 Data Preparation

I used 4 layers of metal wiring with the CMOS process to achieve the LCoS chip line. To this end the first environment in the preparation of Cadence verification tools and match Diva process document (LCoS.tf) [4]. Including: ① LCoS chip lithography version of the definition of layers and their properties; ② symbol components; ③ DRC, ERC, LVS checking rules; ④ parasitic resistance, capacitance extraction rules; ⑤ rules of abstract modules.

3.2 the establishment of LCoS chip display library

The author shows that for the LCoS chip to establish the basic unit includes: inverter, gate circuits, quasi-static D flip-flops, analog electronic switch, the basic op amps, converters, as well as a wide range of applications of I / O unit [5]. Taking into account the basic unit of the logic function is different from an area the size of its territory to be the same, so the direction of the requirements of the basic unit of the same width; and good direction, the basic unit of the same height; and matrix and display the consistent with the rules. This combination of the entire territory, paving the way quickly.

Strategy 3.3 layout

Refers to the layout of modules on a chip placed in the appropriate place and to meet a certain objective function. LCoS display as a result of the overall physical structure of the chip has a strict horizontal or vertical symmetry can be removed from those of conventional semiconductor layout design used in the bottom of the top-level planning and planning. When applying the LCoS chip module shows the physical view of the completion of a one-way or in a separate optimization of the territory can be set up in the Cadence platform intercept LCoS display matrix, and then repeated one-way or in a separate copy of the physical view to achieve the main chip LCoS display layout planning. Figure 3 is a writer in the Cadence platform out of the LCoS (SVGA resolution) shows the chip layout, the figure is designed to intercept pixels 16μm, its diagonal chip to maintain the 21mm (about 0.83 inches) around.

Show the development of LCoS chips

3.4 layout verification

Layout verification task is to check the map errors that may exist. Therefore, the completion of LCoS display chip layout, wiring, the author of the Cadence platform layout verification, including design rule checking, electrical rule checking and layout of the consistency check with the circuit diagram and layout parasitic extraction on the basis of circuit analysis again (that is, after the simulation). In all through the inspection and prove correct, then the result will be converted to layout mask files. Document and then try to mask generated by mask version, usually through the mask version of this generator, or electron beam lithography system.

4-chip micro-physical picture

Figure 4 gives the development of LCoS projection display chip with monochrome photographs of the physical microstructure. This is the use of a domestic semiconductor production lines in the 0.6μm-CMOS process on 6-inch silicon wafer production, the size of each chip 17010μm × 12420μm, which shows the size of matrix 12800μm × 9600μm, which is about 0.63 inches diagonal size. In each 6-inch silicon wafer lithography plane of the effective range of 60 to produce chip LCoS display. Figure 4 (b) is a single LCoS micro-display chip to enlarge photo, which specifically amplified the chip name: NKD-B5, to show the show the self-made chips for domestic production, with China's own intellectual property rights.

Show the development of LCoS chips

5 mirror optical performance test results of electrode

Modulation as a reflective LCoS light valve display, the luminous flux is a key parameter, and the flux depends on the pixel electrode size mirrors, mirror reflectivity and roughness. Display area in a certain case, pixel electrodes directly mirrors the size of the aperture ratio and pixel linear relationship. In this paper, LCoS chip developed by pixel intercept is 16μm, pixel pitch is 0.54μm, the pixel aperture ratio can be:

Show the development of LCoS chips

Figure 5 is different from the thickness of pure Al (99.999%) thin film reflectivity of the test results show that pure Al specular reflectance of the impact of its film thickness. In fact, if the deposition of pure Al film thickness (1μm or more) easily formed "aluminum dome" [6], that is, the emergence of multi-crystalline Al distribution, on the one hand, Al film surface roughness, reducing its rate of specular reflection, and the other will seriously affect the electrical properties of Al films. Thus, according to the above experimental results, this paper using 3000. Thick pure Al film shows the production of LCoS chips specular reflection electrode.

Show the development of LCoS chips

LCoS is currently focused on the development of the industry both in the United States and Britain Fabless companies [7], the domestic in LCoS projector optical engine, light, machine design and LCoS design and manufacture of LCD panels have R & D and the direction of the transfer to the industry trend. What is even more exciting is that our country to enter the LCoS technology did not remain in the system content of low-skilled assembly areas. By Nankai University and other institutions of higher learning, scientific research institutions as a pioneer in funding a variety of channels, with the support of research and development carried out before tomorrow with Chinese own intellectual property rights (IP) shows that the LCoS chip [8]. Can be predicted that LCoS technology in China as the core of the new type of flat panel display industry is about to rise.


1 Robert L. Melcher. LCoS-Microdisplay Technology and Applications. Information Display, 2000; 16 (7): 20 ~ 23

2 Morrissy JH, Pfeiffer M, Schott D, Vithana H. Reflective Microdisplays for Projection or Virtual-View Applications.SID'99 Digest, 1999; 30 (6): 180 ~ 183

3 HCHuang, DDHuang, J. Chen. Optical Modeling of Small Pixels in Reflective Mixed Mode Twisted Nematic Cells, SID '99Digst, 1999, 30 (1): 18 ~ 22

4 Chip Assembly Design Flow Guide. CADENCE Inc., December 1994

5 Yong-Ping Dai, Zhong-Lin Sun, Wei-Dong Geng. Color LCoS micro-display design. Semiconductor Technology, 2001; 26 (10): 37 ~ 39

6 Cacharelis P, Kim U, Frazee J, Moore P, Brown K, Littrell R, Renteln P, Flack R. An 0.8 micron EEPROM Technology Modified for a Reflective PDLC Light-Valve Application.Boston: SID International Symposium Digest of Technical (Papers XXVIII), 1997: 289 ~ 292

7 Chris Chinnock. Microdisplays and Manufacturing Infrastructure Mature at SID2000. Information Display, 2000; 16 (9): 18 ~ 21

8 Dai Yongping, Gen Weidong, Sun Zhonglin.Optimizing the Design for Microdisplay on Silicon, Creating IP Modules for a New Type of SOC. ShangHai: 2001 4th International Conference On ASIC Proceedings, 2001:785 ~ 788

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