ADSP21161 than phase-based ranging radar tracking control system design
Continuous-wave radar with high measurement accuracy, the advantages of simple equipment. Bobby continuous range of continuous-wave radar radar inherited the inherent advantages, the use of technology than the FFT, not only to overcome the general difficulties for the shortcomings of radar range, and also facilitate the use of modern signal processing technology. With the recent development of Low Probability of Intercept Radar needs, increasing its research attention. The introduction of a new digital signal processing devices, not only greatly reduced the radar's own design complexity, and greatly improve the overall performance of the radar.
The main features of 1 ADSP21161
ADSP21161 U.S. AD produced a high-performance 32-bit floating-point processor. In a single chip floating-point operations with a powerful microprocessor core capabilities, 1Mbit of zero wait SRAM, various forms of external interface and a separate I / O controller, form a complete system; Super Harvard architecture (SHARC) and high-speed of the CPU instruction Cache directive makes ADSP21161 are single-cycle instruction; 6 separate sets of procedures are used for bus storage area (PM) and data storage area (DM), can also PM and DM data access; optimized DMA and interrupt the transmission mechanism for making the data exchange with the outside independent and parallel computing processor core in the process;-chip host interface and bus arbiter enables multi-processor without any Additional resources can constitute a multi-processor array. The processor applies to all kinds of high-performance digital signal processing tasks and composition of multi-processor array.
ADSP21161 main features include:
(1) 100MHz core frequency; 600MFLOPS (million floating-point operations per second) of peak floating-point operations; ADSP21161 the completion of a single 1024 point complex FFT takes only 92μs.
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(2) 32-bit single-precision (or 40 extended precision) IEEE floating-point dsp processor core; have three independent calculation of the associated unit (respectively, arithmetic / logic unit, multiplier and shifter); complete arithmetic instruction set computing; with 16 general-purpose register group; all operator instructions are single-cycle instruction; support the implementation of zero-wait cycle and conditions of the transfer.
(3) 2M/1M chip dual-port SRAM zero latency memory, the memory is divided into program memory (PM) and data memory (DM). Dual-port design allows the DSP processor core, DMA controller and the I / O processor can quickly and independently of the memory access.
(4) two sets of the same processing unit, to support the single instruction, multiple data stream (SIMD) architecture; the use of parallel bus architecture, in a cycle, a multiplier can perform ALU operations and one operator, at the same time can also dual-port SRAM read or a write operation.
(5) have the same address two sets of modules, effectively support the SIMD structure, to support the cycle of the buffer addressing, broadcasting anti-load-bit addressing and the addressing sequence, such as addressing a variety of ways, well suited for digital signal processing.
(6) independent of the processor core of the I / O processor with a DMA control, memory map and external communication functions of the processor; 14 DMA channels and with the use of dual-port SRAM, the realization of the internal memory and external memory, external aids, host, serial port, a parallel chain of transmission at the junction between the DSP processor core without affecting the computing process; 8 serial port and 2-chain consisting of point-to-point at the junction of the connection can easily be created by multi - processor system.
Phase 2 of the basic principles of radar range
Bobby continuous range of frequency-domain radar target in the distance, speed and other parameters of the measurement, the basic principle as shown in Figure 1. Firing frequency of the assumption that the two f0, f1 and the frequency difference △ f for continuous sine wave, in which △ f = f1-f0. In order to facilitate the discussion, all signal amplitude are taken as 1. Launch of two component signal voltage waveform can be written as follows:
Due to the Doppler effect, echo signals of the frequency shift. The two echo signal receiver to separate through the mixer, low pass filtering, orthogonal two-channel processing, A / D conversion, the Doppler shift of two signals in discrete time-domain expression of the form:
Where, T for the data sampling period; fdo/fd1 to transmit signals corresponding to the Doppler frequency; c is the speed of light; R0 is the distance between the initial time.
Of x0 (n) and x1 (n) respectively FFF processing, search out the location of peaks. Peaks can be based on the location of the radial velocity to achieve the goal, find the location of the phase peak. The use of the phase difference between the two corresponds to the distance from the target.
3 follow-up control system software and hardware design
Tracking control system in real time given the speed of target, distance, angle and signal to noise ratio and other information, and is able to control the servo system of radar, the radar beam so that the goal has always been tracking live. System design including the design of hardware systems and software systems design.
3.1 Hardware System Design
Tracking control system hardware block diagram shown in Figure 2, which mainly include data latch circuit, FIFO memory circuit, control circuit counts, DSP smallest four major systems, including DSP minimum system also includes ADSP21161, EEPROM and the three main groups SDRAM into a part of.
Data acquisition front-end module on the radar echo data, mixing, filtering, A / D conversion after a series of processing, the output of discrete time-domain signal of the Doppler frequency shift. Front-end data input latch circuit of the discrete Doppler frequency shift signals are latched, it will be necessary to write data FIFO memory circuit. FIFO storage circuit for storing the main data processing ADSP21161 required, it should be controlled by the count of the control circuit. When the count control circuit to achieve set of values, FIFO stop writing data to the DSP control circuit count will send a signal interrupt. The beginning of the measurement, ADSP21161 embedded computer to receive from a group of control parameters, and control circuitry to initialize count. Count in the control circuit to receive the interrupt signal issued, ADSP21161 began to read from the FIFO memory circuit by the pretreatment of the radar echo data, such as FFF and then proceed to a series of digital signal processing, and finally arrive at the target speed, the phase difference and a letter noise ratio and other parameters, and use the host interface ADSP21161 These results will be sent to the embedded computer parameters to calculate the pitch and azimuth angle error to the servo system after so that the radar tracking has always been live targets and real-time display in the terminal objectives relevant parameters. EEPROM for storing the software code ADSP21161 and procedures required for some data. SDRAM is used to solve real-time signal processing chip ADSP21161 the problem of insufficient memory capacity.
3.2 Software System Design
Tracking of software process control system as shown in Figure 3. All the program code is stored in EEPROM, the system after power, ADSP21161 signal through the BMS pin EEPROM auto-load automatic selection procedures.
After the completion of procedures to guide, ADSP21161, first of all, embedded dual-port RAM from the computer to receive a set of control parameters, including number operations, such as FFT. And then count control circuit initialization when the data FIFO to meet computing requirements, ADSP21161 count control circuit to send an interrupt signal, time ADSP21161 began to read from the FIFO memory by pre-processing of data after the echo. Upon completion of data collection, in order to reduce the side-lobe, before computing the FFT of the raw data window, and then began to FFT calculations. Window window function and the necessary calculations required for FFT twiddle factor began to have placed in the EEPROM, in the process after the completion of the use of DMA guide them into SDRAM.
According to the actual use of different, in order to achieve the best effect, you can change the FFT points. 1024-point FFT in the relatively small number, etc., all dealing with the SRAM can be completed at this time using FFT-based time-domain samples of the -2 algorithm. 16384-point FFT, such as in the relatively large number of cases, SRAM capacity is not sufficient to complete all of the processing time, when the first frequency domain using FYT taken, and then taken the time domain, the last re-sort the results in order to obtain the normal FFT output rank .
ADSP21161 direct access to SDRAM. FFF points in the case of relatively large, between the SRAM and SDRAM frequently need to exchange large amounts of data using the CPU direct access to the SDRAM transmitted, whether it is random access to SDRAM row address or access to SDRAM, the highest in the SDRAM working frequency of 166MHz under the circumstances the results of the test takes about 13 orders a data transmission cycle. If the DMA transfer of data, under the same conditions, a data transfer instruction cycle only need one. Moreover, the use of DMA data transfer DMA transfer can take full advantage of parallel computing and CPU, thereby further improving efficiency. In addition, ADSP21161 support chain DMA, can not be interrupted in case of CPU computing multi-stage automatic transmission data. This system, data transfer using DMA mode, as far as possible.
After FFT processing, the radar echo data have been converted to the frequency domain. ADSP21161 further in accordance with the results of FFT to estimate the power spectrum, power spectrum estimation based on the tracking control system to achieve the goal of capturing state to start or follow-up.
Just found the target on the radar when the state can not immediately enter the track. At this time in the target acquisition phase of the radar. At this point, ADSP21161 estimated using the above power spectrum, in the embedded computer sent initial velocity peak search window to calculate signal to noise ratio, signal to noise ratio using a given threshold to determine the current search for an effective peak speed point. If the rate for the effective point of focus is the use of the energy spectrum correction method, the use of correction after the peak position corresponds to the speed of calculation of value, in order to obtain more accurate real-time parameter; if invalid point, then did not find the target radar. In this way, there are several in a row after the effective rate of points, and by the goal of registration in order to capture the success of that goal. In order to prevent low-frequency interference, do not search in the vicinity of zero-frequency peak. Following the success of target acquisition, tracking control system into the stage of target tracking. First of all, depending on the target speed to capture a number of points obtained, using least squares estimates of the speed the next time point values, which predict the rate of participation points and the order of least-squares prediction according to different application of the change. ADSP21161 and then use the estimated speed of the power spectral data and predictive value, predictive value in order to speed-centric search of a range of peaks, using signal to noise ratio threshold to determine whether the current peak as a valid point. Null and void if the speed of a number of successive points, then just lost track of the goal has been, at this time to re-enter the target acquisition system state; if the effective speed of a number of successive points, it indicates that the current on the target tracking radar in good condition. To reduce interference, enhance efficiency and speed can be gradually reduced the scope of search; given speed in order to accurately value, it is necessary to give up from the current measurement of a number of times the speed of time, the only effective use of the speed of a few recent points Forecast for the next time the rate of value.
In addition to the speed of the above-mentioned parameters, ADSP21161 also based on the search to the calculation of the spectral peak pitch phase difference, phase position, signal to noise ratio and other parameters, the final use of the host interface ADSP21161 the results of the calculation of the parameters to the embedded type computer, where the target distance measurement and pitch angle error, azimuth error angle.
After system testing, to the track at the core ADSP21161 control system can be used to complete real-time radar signal processing. Ranging, Velocimetry have achieved relatively high accuracy and can track multiple targets at the same time to the system design requirements.
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