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CPLD in the DSP System Design

Print View , by: iSee ,Total views: 35 ,Word Count: 1822 ,Date: Mon, 24 Aug 2009 Time: 10:01 PM

dsp is faster decoding speed requirements must also be fast. The use of small-scale logic decoding approaches have failed to meet the requirements of DSP systems. At the same time, DSP systems often need to cope with external fast-parts, these parts are often specialized circuits, programmable devices can be achieved. CPLD timing strict fast, programmable, good, very appropriate to achieve decoding and specialized circuitry. In this paper, MAX7000 series, for example, which are detailed in order to TI's TMS320C6202 platform of the network camera system applications.

CPLD in the DSP System Design

1 CPLD in the DSP System Function

1.1 DSP System Introduction

This paper discusses the encoding system is a DSP-based MPEG-4 compression codec, mainly from the front-end video capture, data pre-processing, as well as MPEG-4 video compression coding of three parts. DSP-based MPEG-4 codec DSP of choice because of its computing ability, programming flexibility, and the realization of the different image coding algorithms only need to rewrite the DSP's internal procedures can be achieved, such as MPEG, H. 263 and many other image coding, which has a good application scenario. CPLD chip on the logic control as a whole plays a role in the encoder, the system structure shown in Figure 1.

1.2 CPLD in the system functional requirements

1.2.1 Reset signal

When the system power, CPLD Reset signal so that the whole system FPGA and DSP module reset into the initial state; system power, the data acquisition module starts automatically.

CPLD in the DSP System Design

Three kinds of power within the system were used: 5V, 3.3V, 1.8V. Which, 5V power supply from the power supply access, 3.3V, 1.8V power supply from the TPS56300 (TI products) to provide. Using TPS3307 (TI products) for the system power management, the chip can simultaneously manage three kinds of power. When the monitored voltage falls below a certain value, the generated reset signal. TPS3307 in its own power supply voltage is greater than 1V circumstances that can output the reset signal. 

When the system error, you can use manually reset.

Reset signal generation schematic diagram shown in Figure 2. Which, RST # reset signal for the entire system, the output from the MAX7000. PBSW_RST # for manual reset signal from the key access MAX7000, by the MAX7000 to the jitter of the output to the post-TPS3307. SVS_RST # for power management chips TPS3307 generated reset signal (including the manual reset and power monitoring functions).

1.2.2 BOOT mode to achieve

After a system reset, DSP need to BOOT bootstrap. In the reset signal is low during the period, BOOTMODE [4:0] pin values are latched on the set and decided to chip memory-mapped as well as the bootstrap mode. However, no specific pin TMS320C6202 as BOOTMODE [4:0] input pins, but will extend the bus XD [4:0] maps to BOOTMODE [4:0], the use of pull-up / pull-down resistor reset to chip enable mode settings. Other places are also on the bus is locked during reset determine the appropriate system settings. And the expansion bus XD in the HPI port to use when reading and writing, so I use the MAX7000 isolation. The system at the reset phase, through the MAX7000 allows the value of DSP is equal to the corresponding pin settings reset after the end of, MAX7000 corresponding pin is high impedance state, allowing XD can be used as a normal bus.

DSP bootstrap have specific time requirements. After the reset, XD configuration pin must be maintained for some time, TMS320C6202 required time for five clock cycles, for example, must be kept under 200MHz clock 25ns.

1.2.3 HPI port interface logic to achieve

MPEG-4 compression codec compressed data transmitted through the network transmission control module to the network up, allowing the network real-time image transmission. While the DSP and network transmission module (MCF5272) through the HPI port to connect. Be completed by the CPLD logic of its interface. Hardware wiring diagram shown in Figure 3.

According to the logic of the system requirements and the actual simulation results, CPLD use EPM7128SLC84. The chip is a total of 2500, 128 macrocells, up to 100 user-defined pin.

CPLD in the DSP System Design

2 CPLD logic control of the concrete realization of

2.1 reset signal to achieve

Reset signal logic produces relatively simple, need to be addressed is the button to the jitter. As the button is a mechanical contact, when the mechanical contact is lost, the closing, when there will be jitter, to make every button only once to respond, it is necessary to consider removing the jitter. Through the reset button to obtain the information signal is low when not immediately identified key has been pressed, but when tested again after some time delay reset signal. If still low, indicating keys pressed indeed, this is actually avoided the jitter time when the button is pressed. Similarly, in the post-release button is detected, and then delay a few milliseconds, eliminating trailing edge jitter, and then deal with pairs of keys. As the jitter phenomenon occurred mainly in the button is pressed, the adopted method can effectively reduce the delay jitter phenomenon of buttons.

2.2 BOOT mode to achieve

In order to meet the validity period of reset to configure the corresponding pin in the reset invalid, so that pin into the high-impedance state. To which a pin, for example, using Verilog language, with the following statement to implement this feature:

assign hd0 = (tp4)? rst_hd0: 1'bz;

/ / Reset the validity period, tp4 to 1, hd = rst_hdo, shall set the value; reset invalid, tp4 = 0, hd high-impedance state.

CPLD in the DSP System Design

Because the DSP bootstrap have specific time requirements, at the end of the reset signal, configure the pin must be at least maintain the value of 25ns. Through the reset signal for a certain delay, to meet the demand. CPLD using the signal for a certain delay, and can not simply signal concatenation or other non-door gate, because the development of software in integrated design of these gates will be as redundant logic processing, up less than a delay effect. Therefore, high frequency clock drive a shift register, the shift register is set correctly, the output shall be delayed after the data. Statement is as follows:

always@(posedge eclkout2) //dspclkout=100MHz
begin
if(svs_rst_) //svs_rst_,count1010
begin
count=4′b1010;
end
else if(count==4′b0000) //0000
begin
count=4′b0000;
end //svs_rst_,count
else
begin
count=count+4′b0001; //0000
end
end
assign tp4=count[3];

Simulation results shown in Figure 4. Can be seen from the simulation waveform, CPLD's DSP BOOT signal output in full compliance with the two requirements.

2.3 HPI port interface logic implementation of

Image compression encoder through the DSP's HPI port with the network module connected to the network to achieve the image transfer. TMS320C6202 is with reference to the HPI port expansion bus host port interface part. After the encoder of the MPEG-4 encoded image data to be stored in the frame as a unit in the DSP internal memory, the external host through the HPI port to read. MCF5272 microprocessor is in communication with the HPI port as an example.

CPLD in the DSP System Design

MCF5272 will be a 10/100MB Ethernet controller and USB module and other communications peripherals together, is a highly integrated ColdFire microprocessors. See reference [4].

MCF5272 to connect with the TMS320C6202 asynchronous slave work, MCF5272 as an uplink machine, TMS320C6202 as slaves. Address by the MCF5272 high-wire analog XCNL, XR_W signals, TMS320C6202 multi-purpose serial port 3 work in GPIO mode analog HINT signal, to provide for the MCF5272 interrupt the host mouth. This system consists of CPLD - MAX7000 programming hardware interface between the two. After the timing simulation as shown in Figure 5, experimental proof of the parties to meet timing requirements, to achieve data transmission.

The logic discussed above is not complicated, with 74 series in some extent, also be completed. However, the use of CPLD has the following advantages: the architecture and logic unit flexible, high integration, wide application, which uses CPLD solution.  during the development phase, through the hardware implementation of the control signal often can not determine the need to experiment. The CPLD because of its flexibility, has become indispensable for signal processing DSP coprocessor. Access to the relevant control signal CPLD, only can be realized through a simple programming logic needs to avoid the hardware changes, so that the hardware logic control is more convenient and flexible, of similar design of universal significance. The paper discusses the anti-shake and the CPLD delay program for the similar design also has certain reference significance.

This article describes the CPLD's DSP-based MPEG-4 encoding modules, system application examples have been verified by downloading. Used in engineering practice, the results show that the design is convenient and flexible and correct and effective.


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