DSP-controlled power line communications analog front-end interface design
As electronic technology and network technology, using power lines as a carrier for signal transmission by people more and more attention has been more and more widely used. Power Line is the most common and the most extensive coverage of a physical medium, its power grid is composed of an almost natural physical network. How to use the power grid of the resource potential, without affecting the transmission of electrical energy under the premise of the power transmission network and communication networks into one, making it following the telecommunications, telephone, wireless communications, satellite communications, another after the communication network is a long Technical problems at home and abroad for scientific and technological personnel, a hot spot. Power line carrier communication is in this context that generated it to power grid as a channel for data transmission and information exchange. Power line carrier signal as the transmission medium, is the only investment does not require line of cable communications.
As an emerging communication technology applications, power line carrier communication technology an attractive prospect and potential of its huge market for world attention. China from the last century, 50, began engaging in power line carrier communication technology research. 90 years later, demand for power line carrier technology, along with further expansion of China's economic development. At present, the technology began to be used home automation, remote meter reading, broadband Internet access and other fields. According to experts, in a number of interfering with big, hard wiring to achieve automatic control of industrial areas, using power line carrier communication to achieve a multiplier effect, therefore, power grid has been called "Jinshan has not been excavated."
Power Line Carrier Communication There are many ways, and usually uses a dedicated chip communication system, modulation and demodulation parts and the application of the system while others use another controller to complete, this two-piece method is a good choice. With the digital signal processing technology development, could be combined in a high-level dsp controller can achieve the power line modem function. DSP controller can achieve modem functionality in software, using on-chip peripherals in the power line through the analog terminal interface to achieve to receive and send.
This paper describes is a compliance CEA709  protocol, using fixed-point DSP controller (TMS320LF2812), up from the software and hardware to achieve the power line modem system. The article describes the specific design of analog terminal method, and this terminal transceivers for stability during operation is necessary.
A system framework agreement based on CEA709
Figure 1 shows the physical diagram ANSI/CEA709 protocol standard. A detailed description of the agreement see reference .
Figure 1 CEA709 Physical Layer Block Diagram
In rail transport, network energy management, intelligent buildings, HVAC, coal mine safety, energy and environmental management areas such as the widely used LonWorks control network platform for China's national standard guiding technical documents. Buildings around the world, domestic, industrial and transportation automation industry is based on the LonWorks platform for extensive use. LonWorks platform is the world's largest network of residential smart meter core technology platform, was Sweden, the Netherlands and Australia and other countries of the residential and small commercial meters used by the smart table, while running on this platform control network protocol is the U.S. standard ANSI / CEA709. At present, more and more Chinese manufacturing plant and the integrator used ANSI/CEA709 protocol standards, such as the Qinghai-Tibet Railway - the world's longest high-altitude train, using LonWorks technology platform, using ANSI/CEA709 protocol used for technical monitoring and control of various systems, including monitoring of passengers using the most advanced oxygen supply systems.
For the Figure 1 CEA709 physical layer block diagram, using DSP to achieve CEA709 modem function block diagram shown in Figure 2. DSP (TMS320F2812) with 150 MIPS of computing power, signal acquisition using a 12-bit on-chip analog / digital converter, the conversion speed of 12 Msps, DSP provide PWM to adapt to the power line modem.
Two on-chip PWM output, and a line drive used to implement the sending modem functionality. An A / D input is used to sample a bandpass input signal, thereby to achieve the modem receiver functions, band-pass filter is actually a discrete filter. Them and the exchange of blocking capacitors, transformer-coupled interface with the completion of the analog front-end design. The following introduces the analog front-end interface design process. 2 analog front-end and interface implementation CEA709 communication system to 131.579 kHz carrier frequency to define, for each transmission of data bits from the carrier frequency sine wave on the 24-cycle component, so the baud rate of 5.5 kbps. Segment of each bit can be set phase 0 ° deprived the position of 0, it can be set to 180 ° to make the location one. 2.1 First, remove the coupling network signal reception in the 50/60 Hz power line voltage, and then re-use a second-order active band-pass filter to filter out signals, can detect 131.5 kHz FM signal. This filter is through an op amp to establish. Band-pass filter the output from the DSP's analog / digital converter, a channel sampling, the signal sample sequence by the FIR filter processing, while the output of this filter used for clock recovery and data detection.
Get is a 115 kHz sampling of the received signal, which is the carrier frequency (21/24) times. This signal is 131.5 kHz to 16.5 kHz IF the context of the next sample, then the clock sampling frequency sinusoidal signal mixed with the input carrier multiplication, multiply the results of two sine wave generating two sine wave frequencies "and" and "poor "The synthetic signal shown in Figure 3.
Figure 3 Effect of sampling frequency of post -
Run-time, DSP sample in each ADC conversion is complete will generate an interrupt, and then each sample signals and digital PLL (PhaseLocked Loop PLL) output compared to estimate the received signal phase. In the frequency 5.5 kHz, the phase is determined. If the phase is less than ± 90 °, then it assumes that received a "0" signal, or is "1" signal.
Received bit sequence and the known "bit synchronization" field to compare, when the bit synchronous data received, the modem started to search for "word sync" field. Synchronous data word marks the beginning of message data, but also defines the polarity of the message data. When the packet data determined and 11 decode the code word for the 8-bit data byte, receive byte parity bit and parity bit obtained by calculating the comparison of data from the physical layer transmission to the mac layer. CRC check and then receive the data comparison, the correct data from the data link layer transmission to the network layer.
2.2 Phase Detection
In order to detect transmitted signal "0" or "1", 16.5 kHz IF signal is a discrete phase in the form of received signal values. First of all need to receive the sampling signal drive a digital phase locked loop, when the PLL output has been received signal synchronously locked, the PLL and receive signals between the plural phase estimate is modulated by a phase-locked loop generated. The real part of complex phase is the cosine and, when receiving the "0" signal, it is a big positive values; on the contrary received "1", it is a big negative. The imaginary part of the complex phase is the sine and. It represents the phase-biased, and feedback to the phase-locked loop to adjust the sinusoidal output to track the received signal.
Figure 4 for a complete receiver signal processing block diagram. In order to improve system stability, coupled with an automatic gain control module (Automatic Gain Control, AGC). It is the received signal by detecting the average size to receive the signal. 2.3 signal is sent in the application, send the signal through the on-chip DSP controller, PWM (pulse width modulation module) directly generated. A definition of each of 24 cycles, PWM controller is allowed to run 24 cycles; then, according to the polarity of the next one to send bits through a break to re-assign to the PWM output. To send the message data from the application layer in turn transmitted to the session layer, transport layer, network layer, data link layer, and then to the physical layer, to form to send the waveform. In the data link layer, the message data of the CRC word is calculated that attach to the data, the physical layer to determine whether the channel is available, then the data sent. 2.4 PWM waveform is generated to send the signal waveform by the three DSP controller, the sum of the two PWM outputs obtained, and then the waveform from a low-pass filter to generate a sine wave. Compared with the standard two square wave, 3 wave odd harmonic energy to be much smaller, different pulse widths will produce different harmonic frequencies. In order to filter the harmonics need to be cleared to minimize the need to determine the best pulse width. From the following formula symmetric pulse Fourier series formula, can be found in this width. Type (1) T = fundamental frequency cycle, ω on behalf of pulse width.
So, the total harmonic distortion THD can be expressed by the following formula:
Figure 5 3 wave structure
Pairs of type (2) Find the minimum total harmonic distortion, the best pulse period T is about 37%; However, this has not taken into account the impact of low-pass filter. If second-order low-pass filter, will get different results. In the simulation, the second-order low-pass filter Q is set to 2.3. If the Q large, THD will be better, but it will cause inter-symbol interference, therefore, it is best to set positive and negative digital pulse-width pulse cycle of 1 / 3 length, the low-pass filter corner frequency, and digital pulse sequence set to the same frequency. 1 / 3 pulse-width can be sent through the use of 12 times the waveform frequency of the clock signal timing to obtain, as shown in Figure 5. Through the use of an analog circuit, the two digital signals are added together, and then low-pass filter filter out harmonics, PWM output can be obtained from a sine wave.
Figure 6 to send 2.5 to send low-pass filter amplifier amplifier amplifier design by SallenKey filter to send the decision to send low-pass filter amplifier shown in Figure 6. The transfer function of this circuit are as follows:
Here, R1 = kR, R2 = R, C1 = C, C2 = aC. Suppose amplifier gain of 2, then vout can be expressed as follows:
Q filters at maximum peak maximum, and when the quotient k / (1 + k) is 1, Q maximum.
Therefore, Figure 6 SallenKey Filter resistor R1 and R2 are equal in general, Q determined according to the ratio of capacitors. Send amplifier has two inputs, two input signals from the processor's PWM output from the signal filtering. The peak frequency amplifier to send the greater the harmonic frequency the greater the relative attenuation, therefore, hope that resistors R1, R2, R3 and R4 of the parallel combination of resistors are equal, in order to obtain a larger Q value.
If the definition of R4 = R, then:
In addition, the attenuation factor k defined as follows:
Then, according to R and k to define the resistance value:
The definition of capacitance C1 = C, C2 = aC, according to A, k, a, R and C, to send the amplifier transfer function is as follows:
Given Q, capacitance ratio:
If the amplifier gain A = 2, and take a smaller solution, then the
Finally, s = 0, transfer function gain as follows:
Thus, all the definitions are obtained for the parameters to send amplifier parts, with the above parameters can be designed to simulate the terminal modem. 3 Conclusion This article is only for power-line modem, the hardware design process is described, software design, mainly based on the requirements of the agreement CEA709 accomplished through the DSP. In the design and implementation, there are a number of key technical issues to be addressed, because of space constraints did not elaborate. The fixed-point DSP based on a single hardware modem control in a variety of power under conditions of detection, its function more stable and reliable, are being applied in intelligent home systems.
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