Hierarchical structure of high-speed digital signal processing system design and application of
At present, dsp applications usually require expensive research and development expertise in fan development system, many of which are function and use of special products and the volume is small, their costs are spent on research and development time. For the civilian, time is the market share and money; for the military, time is combat and life. Hierarchical structure of high-speed digital signal processing hardware and software for embedded systems are largely generic, greatly reduces the difficulty of this type of product development and R & D cycle.
A system composed of
1.1 Design ideas
An industrial monitoring and control instrumentation products first need a friendly man-machine interface, real-time data acquisition and control and quasi-real-time high-speed digital signal processing. DSP special chip, while having a powerful digital signal processing functions, but for the man-machine interface design will be limited, if used in hard real-time control is easy to be a simple task to run out of resources. Therefore, the system optimal design is: A small, compact and reliable PCI04 IPC to achieve human-machine interface, high-speed DSP chip quasi-real-time digital signal processing, while the hard real-time signal processing tasks by a complex programmable logic Devices (CPLD) and a dedicated chip (ASIC) to complete.
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1.2 layered system structure
Based on the above ideas, the system should adopt the layered structure shown in Figure 1. Among them, a custom system bus (similar to the GPIB bus) and interface module for the host (level 1) on a number of signal processing modules (levels II, III) monitoring, based on a 16-bit ISA parallel interface design details see Reference . For the monitoring host, the adoption of the debugging stage, you can use alternative to the microcontroller in order to further reduce the size of the weight and reduce costs. In the signal processor module, DSP chips and the composition of RAM and EPROM minimum system constitute the second level, the hardware / software inter-operable. Truly related to the specific product-specific functionality is the third level, it is by the CPLD, ASIC chips, or cascade the work of the application of composition from the processor hardware modules. As the software radio technology and device development, a growing tendency of non-universal sexual function. In the software implementation, while the application hardware modules are mainly high-speed CPLD, partial-speed A / D converter and D / A converters. Therefore, the third level also has a certain degree of generality.
1.3 System Features
After the system architecture at different levels has become more flexible and convenient for extension. For the multi-channel parallel data processing, such as materials sorting, multiple signal processors can be used in parallel structure; for single-channel high-speed data processing, such as radar pulse signal sorting, multiple processors can be used cascade structure. Hierarchical structure of the system and powerful. The third level can handle the nanosecond-level events, such as high-speed pulse signal of the transient parameter measurement; second level can handle microsecond, millisecond-level events, such as digital filtering and parameter estimation algorithms to achieve high accuracy; the first level can handle the non-real time but more complex events, such as the realization of a graphical user interface, archiving printing, database management, and network functions.
The first and second level, the hardware has full versatility, digital signal processor, basic input output software (DSP-BIOS) and its corresponding host interface software is also basically a complete versatile, fully programmable devices also allows the use of the hardware on the third level has a certain versatility. Therefore, using this structure the follow-up product development, R & D work will become increasingly easy and quick.
2 hardware / software co-design process
The above are inter-operable with the hierarchical structure of the high-speed digital signal processing system applied to the specific product design, the first hardware / software functionality and reasonable division, which is actually a hardware / software co-design process, shown in Figure 2 shown.
The first step to determine the function and application specific performance requirements.
The second step, the application independent of any hardware / software functional specification method to describe the system, such as the finite-state automaton (FSM), unified specification language (CSP, HDLs, C, ...) or other graphics-based representation. Its role is to the hardware / software unified representation to facilitate the delineation of functional and integrated.
The third step from the system functional requirements and constraints proceed according to certain algorithms, hardware / software functionality into.
The fourth step is to assess the results of the division. One is the performance evaluation (A), the other is the hardware / software system after a comprehensive evaluation parameters based on an assessment of instruction-level (B). If the results of the assessment does not meet the requirements, the need to repeat the third step, re-division of hardware / software functions, until they are one of the best hardware / software implementation so far.
A large research project done by people need more division of labor cooperation, and indeed the whole of the above for the hardware group and software group assignments done. Carrying out the basic functions of the hardware system debugging at the same time, the software group can write human-machine interface program, database procedures, simulation data and processed off-line version of program. As with the standard language of the actual hardware / software functions described the situation there is distortion of the design phase of the hardware / software functions into sometimes also have some unreasonable, but this can be corrected in the on-line debugging.
3 Key Technologies
In this paper, TI's high-speed processor chips TMS320VC33 to achieve universal digital signal processing embedded systems.
3.1 DSP-BIOS Design
DSP-BIOS software is embedded digital signal processing systems to achieve interoperability of the key. TMS320VC33 the microprocessor (μP) mode, the reset operation after DSP-BIOS software; such as in micro-computer (MP) mode, run after the reset its internal curing Boot-Loader program, and then from the external low-speed RAM or serial Read DSP-BIOS software and transferred to on-chip high-speed CACHE to run at full speed.
A general-purpose DSP-BIOS software should have the following functions:
· DSP initialization;
· Minimum system hardware self-checking;
· With the host computer communication;
· Receiving host computer command and order processing;
· From the host computer to download the application and implementation;
· DSP specific registers settings, such as waiting outside the bus cycles;
· DSP on-chip function blocks (timers, interrupt) control;
. I / O port to read and write (single address);
· Memory read and write (into pieces address).
3.2 system debugging process
Debugging the system generally consists of two processes: the basic functions of debugging and formal applications to debug.
Basic function is to exclude the purpose of debugging hardware system. Exist in the design and production errors, and testing and evaluation of each subsystem (module or chip) of the functionality and performance. Debugging steps are as follows:
· By design, programming and Shaoxie DSP board programmable logic device (CPLD), to confirm CPLD device has been working properly.
· Confirm DSP chip debugging. H1 and H3 signals are all on-chip functional blocks of the synchronous clock timing, is a measure of the key points.
· The DSP-BIOS software burned into Flash-ROM, debug confirm DSP-Boot-Load process. If the BIOS program does not function properly, according to flowchart 3 to debug.
· DSP and PC computer interface debugging. As shown in Figure 1, the hierarchical system structure, the same at level 2 of the number of signal processing module is the multi-block DSP board. The DSP board has a DIP switch settings, "ID" logo, the host sends each command in both yards with a board election, only the "ID" identifies the election code in line with the DSP board will respond to the order. Therefore, the only confirmed that PC normal function of a DSP can be reset and the other controls. Communication the key to debugging is to check the signs and signals.
. Debugging DSP peripherals. Including the DSP board's main memory, the application board (third level) on the RAM, I / O port and ASIC devices, control interfaces.
Formal applications to debug the main objectives are: to exclude application software and applications that exist on-board hardware errors, and testing and evaluation of the entire system functionality and performance. Debugging steps are as follows:
· To debug software and hardware systems for the extraction of a class of subroutine libraries, adding to include the main program interface and database operations, the formation of a formal application to run on-line.
· The entire system functionality and performance testing. When unable to meet the design requirements, analysis of the problem lies, as soon as possible modify application software or hardware, or even re-designed hardware system.
· Streamline the optimization, eliminating redundancy in the design part of the commissioning phase. However, in the process of users is still possible to make higher demands, so always maintain a certain amount of resources remaining is necessary.
4 Application Example
With TMS320VC33 to achieve common hierarchical structure embedded digital signal processing system, which has been successfully applied to a number of military / civilian products.
4.1 Radio Automatic Test Instrument - Single DSP System
Radio communication before leaving the factory, and maintenance repair, we need to test its performance indicators, including frequency response, distortion, signal to noise ratio and so on. In response to this demand for automatic test instrument developed by the radio system architecture shown in Figure 4. The tester hardware system mainly consists of four major components: the digital high-speed signal acquisition circuit, digital signal processors, multi-band multi-mode signal generating circuit and the host computer. Signal Acquisition Circuit applied a high-speed digital down converter HSP50214, the signal generator applied to Digital converter AD9856, DSP in zero-IF signal processing, greatly reduces the processing speed and capacity requirements. And thus a single DSP competent to zero-IF signal on a single narrow-band multi-standard software, modulation and demodulation, filtering and parameter estimation and other digital computing.
4.2 Based on DSP-material sorting system - multi-DSP parallel work
To meet the needs of the market for materials (such as food, minerals, etc.) to conduct quality inspection and sorting of great significance. Sorting is the use of different quality materials, weight, color, size and other physical characteristics of the different principles carried out. According to the theory, developed in our laboratory DSP-based multi-material sorting control system. Early sorting system of domestic intelligence components are used MCS-51 family of microcontrollers, which control functions to meet the basic needs, but its accuracy and pace of work is far from enough, so the system is difficult sorting accuracy of such indicators as so high. In this paper developed a new sorting system uses high-speed floating-point DSP chip TMS320VC33 complete multi-channel signal acquisition and sorting of control, making the work of sorting accuracy and speed have been improved significantly. Each DSP can perform 80 Road 5kHz bandwidth sensor signal analysis and processing, each IPC can manage up to 16 DSP modules working in parallel, thus the total separation speed is very fast. Sorting system block diagram in Figure 5.
4.3 Reconnaissance Radar Countermeasure Signal Processor - DSP cascade over the work of
Radar countermeasures reconnaissance mission is reconnaissance and analysis of enemy radar signals received, in order to interfere with or provide information firepower to destroy enemy radar. Developed for this work based on multi-CPU cascaded signal processing extensions, as shown in Figure 6. It includes: radar signal pre-sorting module, sorting processing module to identify and integrated display modules. In the pre-separation module, a DSP by the first extension from the parameter measurement of high-speed radar video pulse trains were diluted with a rough classification (according to the frequency points), and to describe pulse characters (including the frequency f, direction, pulse rate PA, pulse width PW, time of arrival TOA, etc.) to pass through the dual-port RAM to the DSP to a second separation treatment to separate ministries, the pulse radar signals, which measured their technical parameters. IPC was measured parameters compared with the radar intelligence database to identify enemy radar type, use and threat level, in order to provide a basis for command decisions. By processing speed, transmission speed, storage capacity at all levels of CPU pipeline optimization tasks, bring the whole system to achieve maximum processing power. Results show that the speed has been in line with requirements of actual combat.
Since the hierarchical structure of high-speed digital signal processing systems with a common hardware, software modularity, making successful in a relatively short period of time developed a number of products possible. The next step is to use one of the improvements PCI interface card (for desktop computers in terms of), and USB2.0 interface (on the laptop case) to replace the current ISA interface card in order to improve transmission speed; improvement is to use TMS320C6201 replace the current TMS320VC33, to further improve the processing speed of DSP. However, this paper describes the basic structure of the system hardware and software will continue to be high-end equipment for product development and equipment development preferred.
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