Multi-DSP system, radar polarized signals collection and two pairs of IQ Division
system design background is received and processed L-band pulse narrow-band surveillance radar system, changing the output of the dual polarization modified IQ signals. Dual antenna and down-conversion quadrature demodulation system block diagram shown in Figure 1. IQ level of the signal reflects the level of the radar target echo direction of the reflected amplitude and phase information, the vertical IQ radar target echo signals reflected perpendicular to the direction of the reflected amplitude and phase information. Integrated Dual IQ information, you can get the polarization state of the radar target echo. Polarization processing unit is designed to be the focus of this paper.
A polarization signal acquisition and processing system circuit design
1.1 Circuit Design Overview
Circuit provides a polarization acquisition and processing hardware platform. Functional unit include: sampling and correction, parameter calculation unit patients Feature, the virtual polarization of the weighted unit, according to the measuring unit, master control units, and PCI interfaces.
Circuit diagram shown in Figure 2, Figure 3 below. The circuit is characterized by functional modular, logic programming control. Multi-DSP (4 Pian TMSC5402) at the same time working, flexible and easily achieve a variety of polarization algorithms.
1.2 Acquisition and amplitude and phase correction
Polarization signal acquisition requirements to maintain good four-way signal amplitude and phase coherence. Therefore, four signal through the signal conditioning and AD samples after CPLD1 to do FIR amplitude and phase correction. Amendments include the channel, including the antenna channel vertical degree of inconsistency as well as the quadrature error.
1.3 Bus switch and dsp data sharing
Four digital IQ signals stored in the memory of the DPRAM in the ping-pong from the CPLD to do the bus switching logic, so that polarization data can be DSP1 and DSP2 single time-sharing.
1.4 Polarization characteristic parameter estimation unit (DSP2)
The unit using the polarization of the data collected to estimate the characteristics of targets or clutter polarization. Using TI's C5402DSP completed. TMS320C54x family is TI's TMS320 DSP family of a fixed-point DSP. This series of amendments to the advanced 16-bit Harvard bus architecture, built with a high degree of parallelism of the arithmetic logic unit, dedicated hardware logic, a rich on-chip peripherals and a variety of on-chip memory organization, thanks to six in-depth instruction pipeline, a significant increased level of implementation. The basic parameters are as follows: the clock frequency of 100MHz, a single instruction cycle 10ns, on-chip dual-port RAM (DARAM) 16K words on-chip ROM 4K words. Data / program space for 64K/64K words, there are six DMA channels. DSP2 read digital polarization data, and differences within the window at work, then start the estimation procedure. Estimate the characteristics of the target or clutter polarization, sent to the DPRAM, the time away from the DSP1 unit.
1.5 Phase-weighted units (DSP1)
The polarization of the unit collected data on the virtual weighted. Weights from the polarization characteristics of parameter estimation unit (DSP2). After computing the weighted data through FIFO buffer after, DA output. You can also go to the next one DSP processing unit to do polarization detection.
1.6 Polarization detection and combined units (DSP3)
After receiving the unit DSP1 polarization filtering unit to do the polarization data, making polarization detection algorithm validation. At the same time to do track the merger sent to the FIFO buffer. Through the PCI interface to send explicit control computer, showing effects of polarization operation. The unit also uses C5402DSP completed.
1.7 Master Control Unit (DSP4)
The unit is the total control the entire circuit. display the computer's operating mode to convey instructions to the various sub-units. Observation window of the establishment, by orientation sort and cancellation of work completed by the unit. In addition, the polarization parameter estimation unit results in the adoption of the unit sent to the DPRAM buffer. Significant control computer through the PCI interface to read the polarization parameters. The unit uses TI TMS C5402 complete.
1.8 PCI Interface
PCI interface uses a PLX9054 achieved. Using c model. Significant control computer to read and write FIFO and the DPRAM, communication mode control to achieve polarization parameters and polarization after reading the data read task.
1.9 SDC position unit
The module receives the radar Synchro 400Hz position signal sent through the SDC module converted into digital. CPLD module of the SDC to do digital logic control and direction of the cache. Location information sent to the PCI interface, the way to the display computer; the way sent to the DSP2 unit to determine whether a predetermined manner the work of the window.
1.10 Logic Control
All the logic board control by CPLD or FPGA. Flexible and convenient, easy to modify.
2 The design of several difficult problems
2.1 Bus Switch multi-DSP share data
Figure 4 Methods of chip multi-on-board decoding control, printed circuit board alignment is difficult. Design uses the bus read mode switching and table tennis shown in Figure 5, using a CPLD realization of two DSP on a set of data-sharing.
Is DSP1 to read the above two DPRAM, at the same time, DSP2 read the following two DPRAM. DSP1 data bus is two DPRAM on the cabinets, DSP2 data bus hanging on in the following two DPRAM. When the DSP1 signal SW_EN1 home after reading an application for exchange. Similarly, DSP2 read issued after an application for the exchange of SW_EN2 set. If the SW_EN1 and SW_EN2 are one, that can be exchanged, DSP1 data on-line hanging in the next two DPRAM, while the DSP2 data lines hanging on in the last two DPRAM. Achieve two DSP cross-reading of a set of shared dual-port RAM data. Note: After the switch to generate a signal SW_BUS, two DSP each sample to the signal that can be read another two DPRAM of the data. From the timing can be seen on Figure 6, the bus switch later, the unstable period of about 20ns. Therefore, the receipt of SW_BUS signal 1, DSP delay 20ns to read the other two DPRAM. DSP read operation is preceded by two NOP instructions.
Timing with more than 2.2 DSP
System, there are four DSP, the DSP are to repeat the radar pulse to interrupt the work of the beat, the various sub-task in a radar to complete disruption. Each DSP processing data process are: reading, processing, output. DSP when the DSP is used in front of a few hours after treatment, than the slow rhythm of work in front of a DSP interrupt cycle. Shown in Figure 7, DSP1 processing the first n cycles, DSP3 in dealing with the first n-1 cycle number. DSP1 treated DSP3 Receive FIFO data on, DSP3 processing of data and DSP1 time difference between the data processing time for a break, which is a radar pulse cycle.
2.3 PCI interface to access memory design
Design PLX9054 based data acquisition program; using 9054 C++ model, PCI local side hanging storage methods. To read through the 9054 acquisition PCI bus card stored in the FIFO, the data in the DPRAM. Design work is very simple. The user has done the work of three:
First, burning with the serial EEPROM values. Set up your own system about resource allocation, interrupt and other information requirements.
2 is a PCI local bus address and control lines associated with decoding, gating the corresponding memory.
Third is to use windriver provided driver on the system to prepare to read and write PCI device applications.
In this way, very easy to achieve PCI device data acquisition.
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