TMS320C6202-based compound of active and passive guided the development of signal processing systems
In modern warfare, with the increasingly complex battlefield environment, and a single-guided mode is not well positioned to meet the battlefield in a complex environment with a good tactical performance requirements. Simply the use of active or passive guided simply must always exist, no longer meet the needs of reality. Take the initiative to apply to a wide range of tracking and informative, but once the complexity of electronic systems subject to interference, its performance will be affected, or even completely lost the ability to work; and the passive channel angular precision-guided high, but the lack of distance component. Therefore the use of active-passive composite single-guided-guided technology can make up for deficiencies, to play their respective advantages, through the utilization of information in the performance of the whole system to get each other, thereby enhancing overall system performance.
Passive guided in the main compound in the context of the complexity of the target than I, from complexity order to effectively detect and track the context of goal, we must adopt Romanian complex algorithm; In order to meet the complex requirements of real-time algorithm, the need to use a high-speed dsp chip for system design. TI is currently the company's high-speed fixed-point DSP chip, is the fastest TMS320C64X series, but now only TMS320C64X series commercial-grade chips, can not meet the guidance signal processing environment, so choose TMS320C6202, it can work a maximum frequency of 250MHz, the peak processing speed can be achieved 2000MIPS.
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1 processor function and structure
Processor functions are as follows:
PC provided in accordance with target distance, target angle information, the designated search area.
Environment separate from the multi-objective identification of multiple targets selected.
To the point of view on the target, tracking distance and has anti-jamming features.
The overall structure of the processor as shown in Figure 1.
The entire signal processor by the two signal processing boards and a power supply board, namely the completion of active-channel signal processing and data fusion in active-passive, passive-channel signal processing system as a whole the main power conversion and generation. Between two signal processing boards through synchronous serial communication. In addition, the active signal processing board generated clock and timing signal provided to the passive soft-line signal processing board.
2 system's hardware and software design
2.1 Block diagram of information processing system
Block diagram of signal processor as shown in Figure 2. There are two main channels: channel active and passive channels. Take the initiative to complete the wave channel inside the target detection and passive channels in the entire process to complete the interference detection. And then active and passive channels of information to detect the integration and then tracking the target.
2.2 Information Processing System hardware components
2.2.1 Active signal processing board
The main signal processing board active radar signal to complete the data collection, search and track targets, the active-passive data fusion as well as various timing signals generate. Take the initiative to the structure of signal processing board shown in figure 3.
Active signal processing board using two TMS320C6202, in the standard map DSP0 and DSP1. 2 Apart from the smallest DSP peripheral clock necessary for the system, reset circuit, JTAG debugging extraoral also plug the SBSRAM storage to improve system easily, as well as curing systems used to run the program to guide the FLASH. DSP1 mainly to the completion of data collection pre-processing tasks, so it's expansion bus connected to the six synchronous FIFO, used to store A / D sampling data after the radar echo; DSP0 mainly data fusion and control the completion of the task, it the EMIF bus connected to the low-speed A / D, low-speed D / A, asynchronous serial port, the antenna used to receive and output information and control signals perspective. Between the two DSP through 64KB dual-port RAM for high-speed exchange of data and information McBSP. The use of dual-port RAM is to take into account that it has two sets of data and address bus, very suitable as the interface between the memory system. In general, this design can reduce the burden on a single DSP signal processing, while the entire system has to deal with a certain margin.
TMS320C6202 the EMIF bus need to access many devices, some of which mild electric devices TMS320C6202 signal does not match the speed of the device coupled with a mixture of different visits, so in practice the system need to consider how to allocate the EMIF, as well as storage space by adding an appropriate buffer the problem of isolation. DSP0 here to the external memory interface design described as an example. See Figure 4.
TMS320C6202 largest external space of the EMIF easily 64MB, it is the internal processor is divided into four sub-space, and each sub-space communications to provide an independent election, which is marked in Figure 4 of CE0 ~ CE3.
When the processor is set to boot ROM, the power after the first 64KB read from the CE1 data space to address 0, and then the procedures from the start address of 0, it must be configured in the guide flash address space CE1. No. EPM7128 election communication through access to high address decoder.
CE2 space for through Li EPLD address translation further refinement of the space allocated to the three low-speed devices.
This address space allocation is based on the following considerations:
(1) as a result of TMS320C6202 for each address space can only set up a unified access to the device type and access timing, as far as possible, so the design will pay a visit to the speed of similar devices placed in the same address space, such as low-speed A / D, low-speed D / A as well as step-by-step guide are assigned to serial CE2 space, so the design of the use of EMIF registers.
(2) access to high speed devices in the PCB layout should be as much as possible by the DSP, a buffer smaller series, to reduce the bus delay to improve the access speed.
(3) SBSRAM or SDRAM, as a result of access to higher clock frequency, it should be directly linked in the EMIF bus TMS320C6202.
Figure 4 is added to the isolation circuit is mainly based on the following considerations:
(1) TMS320C6202 its output signal with load capacity is not very strong, increasing the buffer can improve the signal isolation circuit drive capability.
(2) buffer-driven chip when no strobe input and output are in high impedance state, and the input capacitive load is also very small, only a few pF, so the device can be used to isolate and avoid the large capacitive load caused by on red, under the red, the signal increased by slowing down, such as falling edge signal integrity problems.
(3) the output buffer pin chip in the chip are a small series resistance, resistance for the source-side match to attract the signal energy, which could improve the quality of the output signal.
(4) as a result of low-speed A / D chip TMS320C6202 output signal level and the signal level does not match, but the buffer chips are compatible with both the isolation, so the need for isolation buffer.
(5) The TMS320C6202 for BGA packaging, placement and routing in the PCB layout around when space is limited and can be extended by adding isolation buffer distance signal transmission, thus increasing the freedom of PCB layout.
Of course, after adding a buffer isolation will certainly trigger signal transmission delay, thus reducing the speed of access devices, so high-speed devices involved must take full account of this point.
In addition, the design used in two EPLD (EPM7128AETI100-7 and EPM7256144-7), mainly to complete timing signal, chip select signals and control signals generated, so that the system is conducive to the promotion and secondary development.
2.2.2 Passive signal processing board
To deal with the structure of the passive plate as shown in Figure 5. As can be seen is the passive and active signal processing board signal processing board is basically the same type of plate, but, because of the passive signal processing board to deal with the relatively less active signal processing board, so only a TMS320C6202. In order to achieve active and passive signal processing board synchronization, signal processing board will initiate the clock signal, timing and synchronization signals leads to the passive signal processing board.
TMS320C6202 multi-channel serial port for synchronous serial port, as a result of a strong programmability, such as clock, frame synchronization and clock source software can be set up, it is very simple to achieve a maximum of only seven signal lines on the it. Therefore, to achieve through its active and passive signal processing board for data exchange between a small number of very convenient.
2.2.3 Power Supply Board
The whole system needed to supply more variety, there are number of 3.3V, 1.8V, 5V and analog + /-5V, + /-15V. One 3.3V, 1.8-power of a larger power supply, power consumption in the whole system around 18W. Design, in order to avoid the digital signal and analog signals interfere with each other, digital and analog power supply respectively.
2.2.4 Design of the difficulties
Signal processing board design is the difficulty of high frequency digital circuit design and analog / digital hybrid circuit design.
TMS320C6202 work as a result of the frequency of 250MHz, and its external storage devices are also working in a high clock frequency, so when the PCB placement and routing need to consider the issue of signal integrity. In the actual design process, by selecting the appropriate bus topology, a reasonable laminated structure of the high-speed digital signal lines based on the simulation by adding an appropriate reflection of the termination signal to eliminate the problem, solve the signal integrity.
As a result of signal processing on-board analog and digital devices to share and simulation part of the signal level also there is a big difference, such as low-speed A / D converter input signal is between ± 10V, and high-speed A / D converter analog input signal only a few hundred mV, so the design should take full account of which on the one hand, digital circuits to analog circuits interference. In the actual system, to take the device isolation, the rational distribution of components, power supply filtering methods, such as in the op amp and ADC power supply side, the use of ferrite core series to get better filtering effects, analog and digital only at the entrance point in the power connection, and ultimately a better solution to the problem of crosstalk noise, A / D converter to meet the system requirements for both accuracy.
2.3 Information Processing System software design
Processors need to prepare the whole three EPLD software and three DSP. EPLD completed the selection of a variety of timing and control, as well as some simple address decoder, the preparation is not very complicated; software is designed to focus on the functions of the three DSP software distribution and preparation.
The entire signal processing DSP processor as shown in Figure 6. According to the signal processor of the hardware structure and the size of computation of the various DSP functions and processes as follows:
(1) active plate DSP1
DM will use high-speed A / D converter data acquisition read from the FIFO chip. The use of DMA mass number for two reasons: ① High-speed A / D in the FIFO even TMS320C6202 expansion bus (XBUS), the expansion bus in the I / O I work, only the DMA can access, CPU can not read and write ; ② Chuan can use the number of DMA and data processing in parallel, and make full use of DSP processing power.
To read the data and noncoherent CFAR detection.
Extraction of the tracking gate size and angle of error information.
Information will be detected through dual-port RAM to DSP0.
(2) take the initiative to board DSP0
Dual-port RAM from DSP1 to receive the test results.
DSP1 of test results on a second testing.
Test results in accordance with the second state of control switch seeker.
Through low-speed A / D converter to obtain the antenna's angle and speed, through the low-speed A / D converter to control the angle or the speed of the antenna.
Through multi-channel serial port (MCBSP) to receive information on passive detection channel to complete the integration of Active and Passive Information.
Through the asynchronous serial port and the host computer to communicate: send instructors cited the state or to connect the first host computer command.
(3) passive board DSP
The use of DMA read high-speed A / D sampling data.
Detection of the sampling data.
Test results will be sent through the initiative MCBSP board DSP0.
DSP software development in general is divided into three stages: (1) the preparation of c code; (2) If the requirements are not satisfied with real-time, they have to optimize the C++ code; (3) if we do not meet the real-time requirements, will be of critical linear rewrite code compilation. This article is designed to signal processor, as a result of the use of three high-speed parallel processing of DSP chips, together with the procedures of the C manual optimization and TI's C compiler provided with the compiler of a good performance, the whole process is the use of C code, fully able to meet the real-time signal processing requirements.
This article is designed to TMS320C6202 signal processor-core processors have been applied to a seeker of the prototype, and after a field test, performance indicators to meet the system requirements, the results are satisfactory.
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