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TMS320C6205-based signal acquisition and processing system

Print View , by: iSee ,Total views: 26 ,Word Count: 2822 ,Date: Wed, 26 Aug 2009 Time: 10:09 AM

0 Introduction

A typical dsp (digital signal processor) using an improved internal Harvard architecture and pipelining can be completed in a single instruction cycle multiply-add operations, with high processing capabilities. A typical DSP-based signal acquisition and processing systems, often by the DSP, A / D converter, memory, and the corresponding interface circuit, mostly made of PCI (Peripheral Component Interconnect) interface card with the form and master computer. Various control information through the PCI sent to DSP, the results of post-acquisition and processing through the PCI interface, and then sent back to the master computer. PCI-interface chip some of the general need to adopt to complete, this will significantly increase the difficulty of system design debug and make the costs. The choice of their own with a PCI interface, DSP processing chip reducing the need for this part of the additional circuitry, not only reduces development effort, while also lowering equipment costs. TMS320C6205 is such a DSP chip with a PCI interface, this article focuses on signal acquisition based on this chip processing system are implemented.

1 TMS320C6205 chip, the technical characteristics of

TMS320C6205 is based on the TMS320C6000 platform of high-performance DSP, TMS320C6205 from TMS320C6201 B, a new PCI interface and the performance of the DSP chip. TMS320C6205 work in the 200 MHz when the maximum processing capacity reached 1 600 MIPS (million instructions per second). All TMS320C6000 series DSP chips in the code on both compatibility, TMS320C62x fixed-point DSP are based on the same CPU core design, through the instruction parallelism to obtain a relatively strong processing power. The series DSP chip has eight processing units, including two multipliers and 6 ALU (arithmetic logic unit), all of the processing unit can work in parallel, so each one clock cycle up to eight instructions simultaneously.

TMS320C6205 and TMS320C6201 and TMS320C6201B a high degree of compatibility, these types of DSP chips exactly the same in the following areas: TMS320C6205 the CPU and TMS320C6201B identical, so the code can be written for the TMS320C6201 without modification to run in the TMS320C6205; more channel buffered serial port (McBSP), clock, interrupt the same choices; TMS320C6201 and TMS320C6205 of internal storage space are the same, have 64kB of program and data storage area. TMS320C6201, compared with, TMS320C6205 by upgrading with the more processing power, upgraded TMS320C6205 and TMS320C6201 has the following differences:

a) EMIF (extended memory interface bus) made a simple modification to reduce the chip's pins. SDRAM (Synchronous DRAM) and SB-SRAM (synchronous burst SRAM) in the EMIF to share the same control signals. These two signals are mutually exclusive, so in the system only in the two types of memory, alternatively.

b) To improve DMA (direct memory access) data throughput, four-channel DMA controller for each channel is equipped with a dedicated FIFO, so no need to signal to the FIFO arbitration.

c) with the PCI module instead of TMS320C6201B's HPI (host interface), PCI module has a high-performance 32 bit master / slave PCI plug and play function, support for 33 MHz desktop computer with PCI interface, and PCI Local Bus Specification 2.2 compatible, the interface module may be used for 33 MHz, 32 bit width of the PCI master address data from the object to use, the module contains the configuration registers, parity generation, validation, and system error detection and reporting (PERR #, SERR #), as well as power management capabilities.

d) with 4-wire serial interface EEPROM, so that, PCI control space registers can be loaded from an external serial EEPROM configurations, PCI module without DSP intervention can be achieved automatically initialized.

e) TMS320C6205 the PLL are x1, x4, x6, x7, x8, x9, x10, and x11 and other models, these models can be CLKMODE0 pin and EMIF data pins on the push and pull-down resistors to choose.

f) TMS320C6205 using 15C05 (0.15μm) process technology, through the cell processing technology to provide a lower core voltage and power consumption.

g) to spend to push and pull-down resistors to achieve a bootstrap mode configuration.

2 signal acquisition and processing system hardware design

The system hardware mainly by the DSP, FPGA (field programmable gate array) and the memory structure, a specific hardware architecture shown in Figure 1.

TMS320C6205-based signal acquisition and processing system

As can be seen from the figure, the signal acquisition and processing system of the DSP core part of the TMS320C6205 processor, the DSP responsible for signal processing tasks in addition, also responsible for processing the received data and output the results of two tasks. Signal acquisition and processing system in the FPGA mainly responsible for data acquisition and control signals generated two tasks. The system is designed for the receiver demodulator output after the TCL level digital signal, so data collection part of the relatively simple, that is, the data clock as a trigger signal, according to the data trigger time value to determine the level of input data is "0" or "1", after the data collected within the FPGA data in accordance with specifications McBSP framing, and then write to SDRAM in the McBSP. The system can simultaneously capture two-channel digital signal acquisition circuit and the DSP exchange of data between the way through the DMA, because DSP has a dedicated DMA controller, so when the data exchange without DSP intervention, with high processing efficiency. DSP system, the signal is also needed to throw generated by the FPGA, as part of a relatively simple data acquisition, control, signal generation and data acquisition can be shared with an FPCA. DSP via PC interface module and the data exchange between the host, due to PCI interface module with a complete PCI interface functions, without needing an additional external circuitry, the interface part of the circuit design is relatively simple. DSP exchanges data with the IPC used master-slave mode, DSP-based devices, industrial machines from the device using interrupt response between the two data communication, when the DSP within the output data buffer is filled, the sends an interrupt request to the host PCI bus, PCI bus driver responds to the interrupt through the Windows event (Event) to inform host software read data. In order to expand the storage space for DSP, so that DSP can meet the processing requirements of large-rate signal, the signal acquisition at missile system integrates a large capacity memory, that is, SDRAM, with a high speed data access. The signal acquisition and processing system on the flash memory is mainly used to store DSP software is available through the host-side PCI bus, dynamic loading, so that the signal acquisition and processing system can be based on different input data for different treatment, greatly increasing the system uses the time flexibility. The system also includes clock circuits and power circuits, these circuits can refer to technical manual requirements of design, power circuit can choose ready-made power modules, which can further reduce the circuit design more difficult. Overall, the use of TMS320C6205 constitute the signal acquisition and processing system due to eliminating an extra PCI interface circuit, the entire system design more compact development effort is low, the development cycle is short, is an ideal hardware design methods.

3 Based on DSP / BIOS Ⅱ real-time signal processing technology

Signal acquisition and processing system in the DSP not only to achieve high-speed signal processing, also need to address the data input and output, and interrupt request, which must be used in the basic task of scheduling and input and output services, DSP / BIOS real-time infrastructure software provides a small with a base of small to run services, nuclear firmware, developers can embed this core objective of DSP. DSP / BIOS Ⅱ is a performance upgrade of the first two generation of real-time infrastructure software, using the software can reduce the real-time signal processing software development time, and can significantly improve code reusability.

Based on DSP / BIOS Ⅱ signal processing technology to achieve up to make relatively simple, the entire configuration process can use a graphical interface to achieve. First of all, create a new DSP / BIOS configuration file, and then "Syetem" folder, select "MEM", that is, storage area management module, in the MEM module to add two new entries, corresponding to the signal acquisition and processing system SDRAM and Flash memory, SDRAM and Flash memory, set up the base address and length, thus off-chip memory area is set on all complete. As the DSP and data acquisition in part through the McBSP exchange of data, it is also the need for McBSP line settings. Find the "CSL" that is, Chip Support Library folder options in the McBSP under the McBSP configuration management (MsBSP ConfigurationManager) addition of two new McBSP configuration control, these two controls correspond McBSP0 and McBSP1, then set the parameters of these two configuration items, the most critical is to receive mode and output mode settings, receive and output are used non-pressure expansion of the LSB way, there is pressure for the expansion of voice data, you can choose according to μ law or A law pressure expansion, so that the data read and write at the same time, the use of DSP hardware, also completed the μ law or A law companding. McBSP can achieve two-way transmission of data in this system only from the data collection part of the reading of the data were not used in its bi-directional data transfer capabilities. In fact, the use of its bi-directional data transfer capabilities, combined with μ law or A law can easily achieve real-time voice processing. All configurations are set finished, Save the configuration file to join the current project as a whole based on the DSP / BIOS configuration will be completed, in cooperation with the interrupt response functions, we can achieve the real-time processing software development.

Real-time processing software, data flow shown in Figure 2. As can be seen from the figure, the data from the McBSP way through DMA write to SDRAM input buffers, the entire input buffer is divided into a number of films, the data processing section for processing by piece, as McBSP piece of data to write data processed with the DSP chip is not a the same piece of data, data processing and data can be written at the same time, which is to ensure real-time processing of data is a key. Obviously, the more the number of sub-piece of data can have longer processing time, the more suitable for some complex algorithms, such price to be paid is the output of a longer delay, while the DSP chip require large storage space. After the results of data processing stored in the output buffer, output buffer size and enter the same, when the output buffer is filled, the trigger PCI bus interrupt handler, after the results of the processing through the PCI bus master write buffer , the host program from the buffer to read out the data stored to the computer's hard drive the development of file.

TMS320C6205-based signal acquisition and processing system

Clearly, the signal processing software is the most critical software McBSP to DMA interrupt response function and the PCI interrupt response function, the following describes these two functions, respectively.

DMA interrupt response function is the main code is as follows:

TMS320C6205-based signal acquisition and processing system

As can be seen from the code, DMA interrupt response function is the core part is initialized in accordance with the given condition DMA controller, and then start the DMA channel to start receiving data. The main criteria here is to ensure that a given DMA write address to meet the requirements, especially in the case of write cycles will not address conflicts occur. DSP and the host data exchange between the buffer zone is also a way through the interrupt response, and with the way through the DMA read data from the McBSP different, PCI interface to work in burst mode, its interrupt response function in the output buffer will be full filled within the buffer zone all the data written to the host buffer, therefore, no need to slice the output buffer. Such an approach can reduce the PCI interface to read and write times, improve data transmission efficiency.

4 host-based multi-threaded processing technology

DSP data acquisition and processing system processing the results need to output to the host, the host can deal with the results for further processing. The most crucial part of the host program is to read out data from the host buffer, then writes the file on the hard disk. DSP data acquisition and processing system, the driver opened up the host in the computer memory buffer on a host allows multiple data acquisition and processing system to work simultaneously, then simultaneously open multiple buffers. In order to ensure multiple data acquisition and processing system to operate within the host, when used in dealing with multi-threading technology, a whole host processing software development using c + + Builder, in which the development environment is very easy to implement multi-threaded processing technology.

The host processing software core code is as follows:

TMS320C6205-based signal acquisition and processing system

As can be seen from the code, the host multi-threaded processing technology is the core of a thread to execute the function (Execute ()), the function will be writing data to files within the buffer zone, in the multiple data acquisition and processing system at the same time work, The handler function to round robin manner different from the corresponding buffer data is written to the file handle (g_hFiles [i] [0]), which is written to a different file, so as not to conflict with the data write .

In addition to the host program to write data to the specified file, but also can control the data acquisition and processing system for each start and stop, and have online load, and the ability to configure the DSP program, the user can modify the DSP program parameters to perform different processing. All of these features by the system's hardware drivers to provide the hardware drivers have been packaged into a library function, call up more convenient. In this way, the user can be developed according to their different host applications. 5 Conclusion

TMS320C6205-based Data Acquisition and Processing System has been obtained in the practical application of good results, especially the system by loading a different DSP processing for different data processing, greatly expand the scope of application of the system fully reflects on DSP Data Acquisition and Processing System in application flexibility. At the same time as several acquisition and processing system can work simultaneously, the entire processing system can be suitable for different applications need to be competent in different capacity needs.

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