TMS320C6701-based control of multi-chip AD9852 Interface Circuit Design
Direct digital Synthesizer (DDS) because of the short frequency switching time, high frequency resolution, the output phase-continuous, programmable control and all-digital structure, ease of integration, such as superior performance of the radar, communications, electronic countermeasures and other electronic systems more and more widely applied. At present, phased-array radar and multi-channel signal waveform generator and other applications, began to appear at the same time the use of DDS chip multi-chip multi-way synchronization with the output signal waveform of the trend. The author in the three-channel radar IF signal simulator design, the use of digital signal processing chip 3 on the TMS320C6701 DDS chip AD9852 is controlled at the same time the interface circuit to study the AD9852 on-chip multi-chip analog signal output to achieve phase synchronization several key technologies. This article introduced the interface circuit.
About 1 AD9852 and TMS320C6701
The system chosen is a direct frequency synthesizer AD produced AD9852, it can have a frequency, phase, amplitude-controlled high-programmable analog signal stability. At the highest 300MHz system clock, the output frequency range of DC-120MHz, accuracy 1.066μHz, frequency conversion speed up to 1 × 10 8 per second frequency point; with PM and 14 NC NC 12 AM function; with phase shift keying (PSK), frequency sweep function (CHIRP) and frequency shift keying (FSK) function.
The system selected digital signal processing chip (DSP) is a TI company's high-speed floating-point TMS320C6701, its internal CPU integrates eight parallel functional units, with 32 32-bit general-purpose register, it 6ns cycle time up to at the same time the implementation of eight 32-bit instructions, the computing power of up to 1G FLOPS; memory address space for 32-bit, bit addressable 8/16/32; are loaded from the four-channel DMA transfer.
2 TMS320C6701 and AD9852 Interface Circuit
TMS320C6701 is the control center of the system, its main function is to control signals and signal waveform parameters sent to the AD9852 control register within the two block diagram of the interface circuit shown in Figure 1.
Internal control register of the AD9852 can be parallel or serial operation of the read and write. AD9852 serial port because the maximum transmission speed of only 10MHz, while the parallel transfer rate up to as high as 100MHz, in order to improve the dsp to control the speed of the AD9852, the system uses a parallel interface mode, 3 AD9852 8-bit data bus at the same time occupied by DSP data bus of D0 ~ D7, and their address bus 6 at the same time point DSP address bus with the A2 ~ A7 bit. Devices AD9852 chip as a result of the election there is no input signal. Need to use DSP write signal / AWR, chip select signal / CE0 and address data line high resolution A21 ~ A20, and by decoding it to EPLD into WRB NO.1, WRB NO.2 and WRB NO.3 write signal, respectively, the control device 3 AD9852 write signal WRB, the write data bus signal is responsible for the data written to the AD9852's I / O data bus buffer register write data to the AD9852's I / O buffer register in the cache, so that the films selected to achieve a different purpose AD9852 chip.
TMS320C6701 Control EPLD also have a 3 AD9852 needs an external reset signal RESET and clock update EXT I / O UPDATECLK. 3 In order to AD9852 and EPLD synchronization between the system clock, which the external reference clock REFCLK by the same 50MHz crystal to provide the warming.
3 3 AD9852 key synchronization technology
AD9852 in order to achieve three-phase synchronous output signal waveform, we must ensure that all of the AD9852 chip in the same work under the system clock pulse, each AD9852 system clock should be between the maximum phase error of not more than one cycle. AD9852 to form the internal system clock as shown in Figure 2 schematic. AD9852 on the sub-or single-ended reference clock in two forms, they can direct the formation of the system clock, but also through the reference clock frequency multiplier after the formation of the system clock frequency, choose whether the reference clock and through the reference clock frequency multiplier users need to be set up; asynchronous update of the external clock after the edge detection circuit with the system clock synchronized to form a rising edge, touch the contents of the internal control register update. From the above analysis can be seen, only three AD9852 chip reference clock synchronization in order to prevent them from the system clock is not synchronized with each other. Here are three AD9852 chip affected the work of several key synchronization signal.
3.1 reference clock signal
AD9852 chip multi-chip synchronous primary requirement is for each AD9852 input reference clock must have a minimum between the phase difference. Requirements of the system clock signal with a coherent clock sources have four allocated to three EPLD and AD9852, which clock signal to ensure that the drive capacity and the difficulty of bringing the signal integrity. Solution of the system is warming oscillator signal generated by the first sent to a zero-delay clock driver chip input CY2305, and then by the four-chip synchronous clock output signal, which directly supplies the clock all the way EPLD, the other three, respectively, the clock input MAX9371 to the three chips, the chip to enter the single-ended LVTTL-level differential LVPECL clock into the clock level, and then enter the three-chip AD9852. In order to enter a reference to each AD9852 clock signal delay line, require the use of snake-like alignment difference method for wiring carefully, so that PCB reference clock from the same alignment. The system reference clock because the AD9852 differential input mode, not only because it can inhibit the clock signal on the common-mode noise, but it also has the smallest rate and a shorter rise and fall time (less than 1ns).
3.2 update the clock signal
AD9852 control of programming, the write data AD9852 first cache in the internal I / O buffer register does not affect the work of the state of AD9852; AD9852 updates only when the rising edge of the clock signal arrives, the trigger I / O buffer register the data transmitted to the internal control register after the change in the work of the state of AD9852. Update the clock signals generated in two ways, a chip by the AD9852 automatically generated, the user can update the clock frequency of the program to generate a fixed internal update clock cycle; the other is updated by the user to provide an external clock , when the AD9852 I / O UD pin input pin, providing the signal from the external controller.
Will be changed at the same time within the three AD9852 frequency and phase of the process control register recover from illness, in order to prevent the establishment and maintenance of data for reasons of time programming information transmission disorder appears to AD9852 output signal out of sync, the system used by the EPLD provided updated with an external clock signal. If the AD9852 using the internal update mode, although to simplify system design, but because a higher frequency of internal clock AD9852, AD8952 interface will be rate restrictions, to the AD9852 timing control is not easy to control. Update on the external clock signal wiring of the PCB with the same reference clock requirements, we must at the same time it arrived at the rising edge of each AD9852.
3.3 Reset Signal
AD9852 3 of the system use the same reset signal, its power in the system and send control after the data generated by the EPLD, all the registers of the AD9852 is initialized, so that the status of the phase accumulator is set to zero the initial phase so that the output signal of three-phase synchronous AD9852 has a reference point; it also can control the AD9852's internal 14-bit phase adjustment control register, in accordance with the actual needs of the analog output so that they maintain a certain phase difference between signals, which adjust the phase accuracy up to 0.022 °.
3.4 reference clock signal frequency
Low output frequency crystal warming higher cost, when to use it to generate a reference clock signal, the need to use the AD9852 chip reference clock multiplier PLL circuits, the realization of 4 to 20 after the system clock frequency signal, This allows simultaneous multi-chip AD9852 chip work becomes more complicated, because the internal AD9852 has two phase-locked state; locked and locked. In the locked state, the system clock signal and the reference clock input signal can be synchronized. However, when the control commands sent to the AD9852, the reference clock frequency multiplier for a short time after, the phase-locked loop can not be locked immediately, it was locked in, the AD9852 at this time to the phase accumulator of the system clock cycle the number is not controllable, a direct result of three between the AD9852 output signal phase can not be synchronized, so have to wait until the PLL locked state in the future, and then update the AD9852 internal frequency or phase, such as control words. AD9852-chip phase-locked loop typical lock time is about 400μs, as a result of the lock of each AD9852 same time, it is recommended to stay out for at least 1ms to the PLL lock time.
3.5 data bus and address bus signals
The TMS320C6701 data bus and address bus simultaneously with the EPLD and AD9852 is connected to three, in order to enhance the capacity of bus drivers, DSP bus output by TI's chips SN74LVTH162245 drive can interface with the asynchronous connected devices. However, this directly with the number of bus drivers and address of the Ministry of time has been reset AD9852 3 will bring about another potential problem, that is, to reuse the bus between the multi-chip AD9852 provides an electrical coupling with each other channel, their analog output signal isolation between the less than 60dB may be the indicator of the system, it required further improvement. This system is to enable reuse of each TMS320C6701 bus driver signals the first four SN74LVTH162245 input, so that it can be the four outputs of the four were isolated from each other the same signal, and then re-match of their termination resistor increases, the signal path for each match and then received their respective terminals. This will not only solve the problem of signal isolation, but also a good way to solve the signal lines due to drive multi-terminal transmission caused by impedance mismatch problem.
4 AD9852 timing of the operation control
(1) to the system power, DSP control EPLD reset signal generated RESET, this signals the need to maintain at least 10 high reference clock cycle;
(2) to each AD9852 in order to send control characters, so that the work of the state of each AD9852 internal update from the default clock mode into an external clock update mode;
(3) AD9852 clock frequency multiplier to control the work of each word into the AD9852 followed the I / O buffer register, EPLD update external clock generated at the same time update the internal control register of each AD9852;
(4) time to wait at least 1.0ms internal PLL lock AD9852. After the internal phase-locked loop lock, DSP can send the parameters of the signal waveform to each AD9852, the internal control of their content synchronization register updated 3 AD9852 output of the analog signal synchronization.
DDS using DSP control method of the radar signal simulator has been applied, resulting in certification of the simulator output signal waveforms of the three-way synchronization, with high resolution of the distance and speed. In addition, DDS technology allows the flexibility of these programmable features of the simulator structure may also have other applications, as long as the DSP control procedures change, we can have a three-way synchronization of a variety of signal waveforms.
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