TMS320VC5416 Parallel bootstrap realization of the ingenious
With the rapid development of information technology, digital signal processor (DSP) has been widely used. Today's high-speed dsp memory is no longer FLASH-based structure, instead of using faster RAM access to the structure. After the DSP power-down procedures in its internal RAM and data will all lose, so in an environment away from the emulator, DSP chips, after each power-on must be bootstrapped, the external storage area to execute code in some way by moving to an internal storage areas, and automatically. Is widely used at present is that TI's 5000 series of DSP, bootstrap methods are commonly used in parallel bootstrap, serial bootstrap, host interface (HPI) bootstrap and I / O bootstrap. HPI bootstrap need to have a host (such as the microcontroller) to intervene, although they could through the inner workings of the host on the DSP to monitor the situation, but the circuit is complicated and costly; serial bootstrap code is loaded slowly; I / O from the to cite only use one port address, the code kachae fast, but generally require an external memory interface chip to meet the DSP-bootstrap timing, so the circuit is complicated and costly; parallel bootstrap load fast, although the data need to occupy DSP area part of the address, but without adding other interface chip, the circuit simple. Therefore, in TI's 5000 series of DSP in parallel bootstrap has been widely used.
Burn the executable code to an external memory, the traditional approach is to be completed by the programmer. The first use of CCS software in hex500.exe file will be written to convert the *. out file programmer can identify the *. hex file format, and then the programmer will be converted *. hex files burned to the external EEROM in. Then, as the chip manufacturing process continues to improve, more and more integrated chips, memory, being smaller, patch-style direction, a lot of memory chip packages are difficult to programmer programming, much less may frequently plug. EEROM compared with the traditional, flash memory with support for multi-line erase and endurance, high speed, low power consumption, high capacity, low price and so on. At present, many FLASH chip 3.3V single power supply, connect with the DSP without the use of level-shifting chip, so the circuit to connect simple. In-system programming using the system itself directly to the DSP plug-in FLASH memory programming, the programming device to save the cost and development time, makes the DSP implementation of the code can be updated online.
Here, in the executable code in the FLASH burning is no longer used hex500.exe documents *. out files to convert, but Miao cleverly used "two downloads Law," the use of DSP to the FLASH write operation will be enforceable FLASH plug-in code to go directly to write.
In this paper, a TMS320VC5416 plug-in a SST69VF200 FLASH memory, for example, describes how the DSP-system programming of FLASH in order to achieve a specific DSP parallel bootstrap method, and gives part of the DSP-C program source code.
1 DSP and FLASH system composed of bootstrap
DSP in the bootstrap process, is the external storage area as a data store to visit. Therefore, in the design, although the internal FLASH memory is the code, but still the data in terms of DSP. As the TMS320VC5416 data bus is 16 bits, so the choice of a 16-bit bus interface FLASH memory. Data area in the 0x0000 ~ 0x7FFF corresponds to the DSP memory RAM area, so the DSP to the external FLASH operation can only access 0x8000 ~ 0xFFF of the 32K word storage area.
DSP bootstrap the system's basic connection shown in Figure 1. Bootstrap system FLASH chosen for the SST's SS39VF200, the FLASH memory capacity of 128K words, 16-bit bus interface. For simplicity, the figure does not deal with FLASH for paging, simply regard it as an external data store to deal with. As SS39VF200 read signal OE and the write signal WE is separate from, and write signals take precedence over read signal, while the read-write DSP share a pin, so it's read-write DSP write signal and the signal FLASH connected while its reading of the signal OE direct ground, FLASH chip select signal CE data directly with the DSP-area selection signal OE is connected, which indicates that the FLASH data storage area as a DSP for a visit. As noted above, DSP only have access to external data area 0x8000 ~ 0xFFF regional data, so for the 39VF200, the highest bit address A16 can be directly grounded. For the above-mentioned circuit connection method, 39VF200 from 0x0000 start 32K memory space is not accessible.
2 TMS320VC5416 in-system programming for SST39VF200
2.1 SS39VF200 Chip Description
SST39VF200 operation unlike ordinary RAM and ROM, in addition, like the process of reading the data, all other operations are not the same, must follow a certain order to perform.
2.2 TMS320VC5416 right SST39VF200 programming operation
Typically, right before FLASH programming must be written in FLASH in the region to be erased before programming operation. Note that each issue of the FLASH operation commands, you must wait until the FLASH to complete this operation in order to send the next operation command. FLASH the command is completed to determine the implementation of two ways, one using data bits D7 to determine, if the FLASH operation has not been completed, then read the bit is always low, finished after the position becomes high; the second is the use of data bits D6 to determine If the FLASH operation has not been completed, then the two adjacent read the value of D6 bit different. When the two D6-bit values read are the same, indicating the completion of this FLASH operations.
The following data bit D6 in order to determine whether or not the operation is complete, indicating TMS320VC5416 right SST39VF200 write the specific process, and other operating process and the process is basically the same.
Void Word_Program(uint * Ad,uint DQ) //Ad，DQ
uint *Ad_Temp,Temp1,Temp2; //
Ad_Temp=(uint *)(0x55555); //
Ad_Temp=(uint *)(0x2AAA); //
Ad_Temp=(uint *)(0x5555); //
Again;Temp1=*Ad & 0x0040; //D6（Toggle Bit）
Temp2=*Ad & 0x0040;
If(Temp1!=Temp2) //，Toggle Bit
3 TMS320VC5416 Parallel bootstrap
In-system programming can be achieved through the implementation of the code is written to FLASH. If it is determined in the user program FLASH memory format code and correct the bootstrap in order to achieve off-line operations are the focus of the entire in-system programming.
Table 3.1 Bootstrap
Introducing the DSP parallel bootstrap process must be preceded by DSP-bootstrap table to illustrate this. The need for DSP bootstrap table to illustrate this. Need to bootstrap the table in accordance with the provisions of TI's format to create. The table stored in the DSP initialization to the use of special registers, such as SWWSR, BSCR and so the value of the program entry address, the first address of the target segment and the length of and the need to implement the code.
3.2 and know the process of bootstrapping
A complete parallel bootstrap flowchart shown in Figure 2.
SST39VF200 FLASH memory is 16 bits, so the actual use of the 16-bit parallel bootstrap, DSP internal bootloader reads from the data space address 0xFFFF bootstrap table in the first address, the final table from the bootstrap executable code will be moved to the DSP the corresponding RAM.
3.3 "two to download Law" to achieve a parallel bootstrap
How to bootstrap in accordance with provisions of the table format the various elements of the table is written to the FLASH plug-in go? Common practice is to use hex200.exe file *. out files converted *. hex format, and then read the *. hex file, writes FLASH. Here is more convenient to adopt a "two to download the Law" will write the bootstrap table FLASH, the whole process without file conversion and file read and complete this process, the code is very small, takes up little storage space within the DSP.
The so-called "two to download Law" is through the simulator of the DSP loaded twice to complete the bootstrap table creation. The first load the users want to bootstrap executable code, known as code 1, loading exhausted does not run this code; followed by the establishment of bootstrap loading code for the table, known as code 2. Code 1 is the DSP offline run-time code, code 2 is only the code a bootstrap table in accordance with the format to the external FLASH is written in code. Note that the code and code 2 in the allocation of a program memory space can not overlap, but the code must contain two of the data space and the external FLASH code is a common occupation of space, because it is necessary to code a way to access the data by writing to the external FLASH in. As the downloaded code is not followed by a run, but to download the code followed by 2, the two procedures for storage area and do not overlap, so downloaded code 2, the previously downloaded the code in a still in the DSP, but only look at the code 2 into the data only. "Twice to download Law" concrete steps are as follows:
(1) DSP-MP / MC pin set high, so that work in the microprocessor DSP mode.
(2) code in an emulator downloaded to the DSP through, but does not run the code.
(3) Code 2 download to DSP through the emulator, run this code.
(4) code two runs after removing the emulator, and MP / MC pin set low, so that work in the micro-computer DSP mode.
(5) Reset DSP, observe whether the results of program runs correctly.
"Twice to download Law" twice in the code storage area distribution shown in Figure 3.
The figure, the code in a data segment starting address 0xA, data segment end address this 0xB, code segment starting address 0xC, code segment end address of 0xD, which 0xB and 0xC may be the same address, but different address ; code 2 in the data segment start address 0xG, the end of data segment address of 0xFFFF, code segment starting address 0xE, an end address of code segment 0xF, which 0xF and 0xG may be the same address can also be a different address. For TMS320VC5416 is concerned, because 0x0000 ~ 0x7FFF corresponds to the 32K words of internal space, so the size of the two tables in the address relationship 0xG <0xC <0xD <0x8000.
Based on the above idea, assuming that the code of a program segment for the 0x4000 ~ 0x7FFF, the data segment is 0x3000 ~ 0x3FFF, the code segment for the two procedures 0x2000 ~ 0x2FFF, the data segment is 0x3000 ~ 0xFF7F (Note that the code must be two of the data segment The code contains a code segment and address space occupied by FLASH, code 2, code segment must not be a code segment and code overlap), external FLASH occupy the address space 0x8000 ~ 0xFF7F, bootstrap table in the first address from 0x8000 started and SWWSR and the value of BSCR, respectively 0x0E38 and 0x8806, the program entry address 0x004089, code is a length of 16K words, the code a storage start address 0x004000, then the code in the FLASH to create two bootstrap procedures are as follows table :
UINT I; //
UINT *Addr1,*Addr2; //
Addr1=(uint *)0x8000; //
Addr2=(uint *)0x4000 //1
Code 2 In addition to the above bootstrap the establishment of the table also included the FLASH erase and bootstrap data validation tables. Important to note that, in the FLASH write operation, you must erase them, erase part of the program can refer to the previous Word_Program () subroutine.
In this way, through a simple "two downloads Law," the use of the code 2 will be offline to run the code in a self-written to give the format of the FLASH memory, the checksum is correct DSP can be off-line work.
Use of "two to download the Law" using DSP's own FLASH programming, enabling the parallel DSP bootstrap. This in-system programming of the DSP bootstrap implementation is simple and flexible. In this paper, the hardware circuit only applies to the program code is less than 32K words of the system. In general DSP systems, FPGA and other programmable devices will have to use their flexibility to paging operation of the FLASH. Thus, in the process of more than 32K words, this method is also applicable.
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