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64-bit data with error correction function of Frederick FPGA module design

Print View , by: iSee ,Total views: 23 ,Word Count: 2056 ,Date: Wed, 24 Jun 2009 Time: 5:24 PM

0 Introduction

With the development of modern technology, as the representative of modern high-tech aerospace engineering, computer on-board dependence on increasingly high. Due to the existence of the universe, a large number of charged particles, the computer hardware on-board electronics system will be electromagnetic radiation and heavy particle impact, the interaction of various effects, including single-particle inversion (SEU) effects is particularly that it will work cause satellite anomalies or failures. SEU is caused by space radiation environment, heavy ion track movement around the charge generated by the collection of sensitive electrode, the formation of the transient current, trigger logic circuit, leading to the logical state of flip, causing misoperation, making on-board computer data may small probability of error, which occurred in the main memory and logic circuits, resulting in the contents of memory cell turnover occurred (1 to 0, or O to 1). This error does not promptly corrected, will affect the operation of computer systems and the accuracy of critical data, resulting in running the state of instability and change equipment. Found the use of error-correcting code error correction circuit design is an on-board computer so that SRAM has an effective anti-SEU method, which can reduce the probability of data errors and protect the normal operation of computer systems.

1 Error Correction Principle

Hamming code (Hamming Code) by Richard Hamming in 1950 and made belonging to the scope of linear block codes, the basic principle is that information and monitoring symbol symbol linked through a linear equation, and every bit of an oversight by code word for transmission of the specific bit position. System for the mistake of digital information whether it is the original place of, or additional supervision in place it can be separated. (n, k) linear block code to generate the check matrix of matrix G and H are n × k and n × (nk)-dimensional matrix, which decided to check the information bit matrix H and the relationship between the parity bit in the encoding and should be used in decoding. Linear code the minimum code distance for d, that is, any check matrix H in the d-1 linear out has nothing to do with the error correction code has the following relationship between the ability to:

(1) Detection of P random error, request d ≥ e +1;

(2) correct t random errors, require d ≥ 2t +1;

(3) correct t random errors, while detection of e (e ≥ t +1) random errors, the requirements d ≥ e + t +1.

As a typical linear block codes, Hamming code standards of the code length n = 2m-1, supervision median m, the information median k = nm, the minimum code distance d = 3, so its error correction ability t = 1, is a commonly used single-bit error correction encoding. Can also be in accordance with the standards need to be extended Hamming code, an increase of a parity bit of all the monitoring, it has been extended Hamming code. A (n, k) Hamming code, after expansion, would be turned into a (n +1, k) Hamming code. Extended Hamming code after d = 4, t = 2, e = 1, can correct single-bit errors and detects double-bit errors. On 64-bit error correction data designed to meet the information requirements of the median is greater than 64 minimum hamming code for the standard n = 26-1 at the time (127,120) code, it has a parity bit 7 supervision. According to the information-bit hamming code error correction ability to cut after not lower than before the characteristics of the information that the code be shortened to 64-bit, use the (71,64) Hamming code of the deletion. Here the design of a 7-bit checksum information with the 64-bit computing corresponding relations as shown in Figure 1.

64-bit data with error correction function of Frederick FPGA module design

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Figure 1 DA0 ~ DA63 place for information; CC0 ~ CC6 to oversee the parity bit. CCO which is all located in the bottom number in a number of information bits of data parity calculations. Similarly, CCl number corresponds to all time low at a number of informative sites. Similarly, CC3 ~ CC6 a line number corresponding to that line number is 1-bit data information. Through this correlation table, we can draw a whole generation of hamming code formula:

M = DG

Where: M is generated (71,64) Hamming code matrix, each row vector is a set of Hamming code; D matrix for the information-bit data line, 64-bit of information to form a row vector; G be the hamming code matrix to generate can be calculated in accordance with the corresponding relationship between the above-mentioned works.

When the implementation of error-correcting functions, need to read the data bit and supervision parity bit, and read data on the parity bit in accordance with the Algorithm 1 re-generation of parity bit (can be used to NCC0 ~ NCC6 said), through the CC0 ~ CC6 and NCCO ~ NCC6 the ratio of Error Detection and Correction for computing. If a data flip error, the new generation of the parity bit will be a number of NCC in the C++ with the original parity bit different, and the adoption of different data-bit error correction can be. The assumption that the current detected in CCl, CC2, CC4, CC5 This parity bit 4 of the NCC with the new generation of the corresponding XOR-bit computing results for the 1, Figure 2, shown in small arrows.

64-bit data with error correction function of Frederick FPGA module design

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CCl Parity error data corresponding to different ranks second in the countdown to No. 1; CC2 listed corresponds to the penultimate 3 No. 1, you can launch out of the wrong data bit number is 110, same line number in several school-related inspection position in CC4, CC5 appears different data bit errors can be introduced line number for 0110, which can know the data error is the DA22, a further confirmation of the data bit error check on the achievement of the correct anti-a wrong function. If two errors occur, such as the data bit error at the same time DAl and DA34, as shown in Figure 2, which give rise to new and old parity bit in the CC0, CCl, CC3, CC4, CC6 different at the same time. At this time if it is corrected in accordance with the above error at the time of an algorithm, will be the introduction of data bit errors for the line number for the 1011 No. 011, so that data will be considered to be overturned DA51 occurred, resulting in the seizure wrong correcting the results in Figure 2, shown in thick arrows. Previous test data show that, if in near-Earth orbit, SRAM memory storage for each data bit in one day about the probability of occurrence of SEU is 10-7 (digital days), it can be derived from the SRAM in group 1 64 data, the time of the day, there are two at the same time the possibility of error is about 10-10 (at days), radiation in the South Atlantic anomaly and the peak of solar activity, the incidence of such cases may also be increased by 1 ~ 2 orders of magnitude.

In order to avoid in the event of an error when double-byte error correct the wrong situation, the need to increase a parity bit CC7, it is all the data parity bit, that is, CC7 = DA0 ⊕ DAl ⊕ DA2 ⊕ DA3 ⊕ ... ⊕ DA63. So that every time a data bit error, the new generation will NCC7 also differences with the previous value, and when the data bit in the two memory cell errors, and other parity bit will detect an error, but NCC7 will not change, NCC7 ⊕ CC7 = 0, then we can determine a double-error, thus allowing the system to achieve a double-error detection function.

2 Design and Implementation

All data in main memory and the one-to-one parity bit (CCl ~ CC8) are stored in separate 8-bit SRAM, the system's hardware structure shown in figure 3.

64-bit data with error correction function of Frederick FPGA module design

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Check store 8-bit data SRAM2 same SEU effects encountered were likely to arise through the analysis, we can know, SRAM2 occur when a data inversion, and only one of the corresponding numerical data and new parity bit generated by numerical phase differences, and the other 7-bit data checksum has not changed at this time of the corresponding parity bit to achieve a counter-check error-correcting function. Double-bit errors for the possibility of theoretical analysis, we can see that a group of 8-bit checksum of data in a single day in the probability of such a situation is about 7 × 10-13. Compared with that in the main memory 23 in terms of lower order of magnitude, the time being can not be considered.

FPGA logic design error correction of the seizure using VHDL language. Design SRAMl main memory of 64-bit data of the new generation of NCC [7:0] and 7 of SRAM2 parity bit CC [7:0] together after XOR operation to generate the correction sub-8, of which 7 place on the position error corresponding to the aforementioned data and the line out the value of its first 8-bit to determine whether there is a double-byte errors. 8-bit checksum value can be obtained son a 64-bit Error Correction Mask (Mask), to error correction unit. If no error is detected, the mask bit are all zero. If the unit detects an error, the corresponding mask bit will be outside the shield in addition to all the wrong places. The next stage, the use of raw data for this mask XOR operator. Ultimately, the error bit to be inverted (or correction) to correct the state. If double-byte error is detected, all have zero mask bit. 1 pairs of the use of the array bit (ER [1, O]) for reporting the type of error detection ( "OO" had no right or wrong, "01" units that error, "10", said double-error, "11," said can not determine the number of errors). The work of the whole process of error correction logic shown in Figure 4. Report generated an array of error types and the corresponding mask correction of the work completed in the same clock cycle, reflects the use of FPGA for parallel processing of unique advantages.

64-bit data with error correction function of Frederick FPGA module design

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3 Conclusion

After the integrated analysis of simulation results, artificially joined during the 1, 2, 3 random distribution of data bit errors, the system clock cycle in the two systems on an error detection and successful correct; of two and three error conditions are also carried out to determine the correct category. The simulation results show that the ideal system designed to meet the design requirements.

However, for the whole-board computer system, the space in very harsh environments, the impact of radiation and particle impact must not only in the SRAM on the FPGA, dsp and other chips will also have the same impact on all kinds of complicated, it is necessary to Elimination of these effects to ensure that computer systems work reliably, but also the needs of the majority of scientific and technological workers a lot of work.


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