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Based on Dynamic Reconfigurable FPGA System Design and Implementation

Print View , by: iSee ,Total views: 28 ,Word Count: 3175 ,Date: Fri, 26 Jun 2009 Time: 5:26 AM

0 Introduction

Due to the complexity of digital logic function of the demand for chip-chip system is moving in ultra-large-scale, high-density development. For a large-scale digital systems, the system is based on the size of the various combinations of logic function modules. However, both the temporal logic system, or combination of the logic of the system, or combination / sequential hybrid systems, from a timeline point of view, the system function modules are not all work all the time, but overall the system of external requirements, rotation or cycle to be activated or work. And, with the expansion of digital logic, the speed in the same conditions, at a certain time interval, the function modules of the average utilization rate will drop. Therefore, the system should be designed to seek from the traditional large-scale, high-density direction, towards how to improve the utilization rate of resources, with limited resources to achieve a large-scale logic design table. Reconfigurable computing technology can provide the efficiency of hardware and software programmability, it combines the characteristics of microprocessors and ASIC, in the space dimension and time dimension can be changed on.

1 Reconfigurable Technology

1.1 Re-definition of

Reconfigurable electronic system is in working condition, the dynamic changes in the structure of the circuit. This is mainly through the system re-programmable logic device configuration or partial re-configuration to complete. The use of reconfigurable technology, only a slight increase in hardware resources, the system also has software and hardware to achieve the advantages.

1.2 Re-way classification

Manner in accordance with the reconstruction, the system can be divided into static system reconstruction Reconstruction (Static Reconfiguration) and dynamic system reconfiguration (Dynamic Reconfiguration).

1.2.1 Reconstruction of a static system

Reconstruction of the static system is the logical target system static overloaded function can only be run before the system configuration, as shown in Figure 1.

Based on Dynamic Reconfigurable FPGA System Design and Implementation

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FPGA function under the control of external logic through stored in the memory of the target system with different data re-download in order to achieve changes in the chip logic function.

1.2.2 Dynamic System Reconfiguration

Reconstruction of dynamic system refers to the process in the run-time reconfigurable system configuration, as shown in Figure 2.

Based on Dynamic Reconfigurable FPGA System Design and Implementation

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Changes in the timing of the digital logic system, the occurrence of temporal logic by calling the chip rather than in different regions, different combination of logic resources, but by specialized cache with FPGA logic resources to carry out, in part or in whole dynamic logic chips Reconstruction and quickly achieved. FPGA dynamic system with the structure of the logical cache (Cache Logic), the external control logic through the logic of the cache logic chip or in part, the rapid global changes through re-placement and routing control of the allocation of resources to accelerate the achievement of system of dynamic reconfiguration. The realization of dynamic reconfiguration on a different area, but also can be divided into the overall reconstruction and partial reconstruction.

(1) the overall reconstruction. On the FPGA device or system can only be carried out and all the re-configuration. In the configuration process, the calculation must be taken out of the intermediate results stored in the additional storage area until the new configuration features all the download finished, the before and after reconstruction of the circuit independent of each other, there is no correlation.

(2) partial reconstruction. Device or system for the reconstruction of the partial re-configuration, at the same time, the rest of the work of local state is not affected. Reconstruction of partial reconstruction of the scope and reduce the number of units, greatly shortening the reconstruction time, a considerable advantage.

2 Dynamic partial FPGA-based Reconfigurable Technology

2.1 has a partial function of dynamic reconfigurable FPGA

It is generally the last dynamic reconfiguration of the FPGA's main XC6200 series of Xilinx and Atmel's AT6000 series. They are also the SRAM-based structure, but all SRAM cells can configure a separate visit, that is, partial reconstruction. their functions, which have the characteristics of partial reconfiguration. The advantages of doing so significantly, but it can also pay a larger circuit size and power consumption of hardware cost. Ultimately to achieve the full real-time electronic system reconstruction should be used in the structure of dynamic partial reconfiguration of the FPGA device features, such as Xilinx's Virtex-4 series.

2.2 Based on Local Dynamic Reconfigurable FPGA technology and the typical characteristics of the principle of

Partially reconfigurable FPGA dynamic characteristics of technology is to the overall timing according to the functions or broken down into different combinations, and in accordance with the actual needs of local time on-chip dynamic reconfiguration, with less hardware resources to achieve greater timing system overall function. Figure 3 gives a typical dynamic partial reconfigurable FPGA. As can be seen from Figure 3, the external control logic can be of real-time dynamic partial reconfigurable logic chips. By controlling the layout, routing resources, the realization of the system dynamic reconfiguration.

Based on Dynamic Reconfigurable FPGA System Design and Implementation

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2.3 FPGA realization of the local dynamic structure of reconfigurable

For effective implementation of FPGA dynamic reconfiguration of real-time systems, FPGA in the structure must meet the following requirements:

(1) not only has the ability to be re-programmed at the same time the dynamics of re-allocation of system resources and will not damage the device or in part, the logic of the overall operational capability. Many traditional FPGA configuration data stored in the external EPROM in the serial. This approach has three shortcomings: Reconfigurable FPGA must be stopped before the entire work; only reconstructed the entire FPGA; reconfigurable FPGA in the past when the internal state can not be saved. To achieve a new dynamic reconfigurable FPGA reconfiguration before do not need to reset the trigger signal, but a FPGA chip local clock logic circuit to close, and then re-configure the logic circuit, and finally the restoration of the clock signal.

(2) FPGA internal configuration information symmetry, recorded at any time, any general-purpose basic logic function can be configured in the device of any one location, using a simple model based portfolio to realize the complexity of functional juice.

3 Reconfigurable FPGA-based presentation system design and implementation of

3.1 Demonstration of the hardware components to verify system functions and

(1) demonstration of the hardware verification system, shown in Figure 4. ARM processor chip with 256 KB on-chip SRAM memory, 2 MB memory capacity FLAsH. Mainly sPARTEN-3AN family control FPGA, to control their access to the reconstruction of flash program memory; FLAsH Memory ARM through the parallel data into serial; ARM in the built-in memory used to store FLAsH procedures;

Based on Dynamic Reconfigurable FPGA System Design and Implementation

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(2) SPARTEN3AN series FPGA, is based on the non-volatile memory of the FPGA, mainly as a PCI bus and between the ARM processor dual-port; placed Spw IP core, UART IP core, 1553 IP core; simulation JTAG port;

(3) two XCVSX55 the FPGA dedicated JTAG, configuration file download. Xilinx FPGA based on SRAM technology, it is volatile in nature. If you turn off the power supply device, its configuration will be lost. In the production environment, FPGA typically use external memory (eg PROM) to prevent loss of configuration data when power failure;

(4) FLASH memory capacity of 16 M × 32 b, for the processor power and storage of a number of guidance modules for reconfigurable FPGA-level programs;

(5) the two PROM-XCF32P. Virtex4 series XC4-VSX55FPGA, its configuration PROM for XCF32P, 32 Mb memory capacity. The use of the design XCF32P Amendment (Design.Revisiorling) feature a variety of FPGA configuration storage for different versions of the amendment in order to simplify the FPGA configuration changes. Power, the configuration PROM from the internal logic of the revised version of the design input (pins or control bits) for sampling;

(6) two test lines, four in each group, cl_Test [3. . O] and C2-Testl [3. . O], respectively, the two test XCVSX55 series FPGA Reconstruction Reconstruction and feedback results;

(7) two-channel line of the PROM control signals, C1 (C2) _PROG, C1 (C2) _DIN, C1 (C2) _DONE, C1 (C2) _INT, C1 (C2) _CCLK to achieve two XCVSX55 series FPGA-PROM way to download. Since the JTAG (boundary scan) chain in which the event of the failure of a component of the JTAG chain will affect the normal function, so use: PROM download standby mode;

(8) all the way RS-232 receiver drive to achieve and external communications interface;

(9) PCI bus, the bus through the computer interaction with the outside world and external interfaces.

3.2 Demonstration of the working principle of verification system

3.2.1 Power-on reset

In the power-on reset, the ARM and the FPGA to ensure that synchronous reset. Xilinx's FPGA power around 200 ms is required to configure the time, during which I / O pin in a three-state status, and therefore the key to the input / output signals (such as IRQx, NWAIT, 2.56 trillion output data and output clock) on the need for the drop-down to ensure that the ARM and the external interface signal in the normal state, to avoid signal conflict.

3.2.2 Initialization

Initialize the main part of the work of 2, respectively, completed by the ARM and FPGA.

(1) ARM implementation of the initialization work. Bootstrap control procedures, including monitoring procedures → ARM → internal register is initialized to load the hardware self-test markers → → (to load software updates) → FPGA parameters → user software to load and check the integrity of the correctness of control → the right to ask the user to initialize user software → software → software users.

(2) FPGA implementation of the initialization work. Main FPGA logic state of the internal registers and the initial value of zero to rely on internal data buffer to complete the reset signal. One of the "FPGA parameters" responsible for the implementation of the monitoring program or by the use of default parameters to complete FPGA. Data fusion format, input / output code rate parameters stored in the FPGA, such as the ARM chip FLASH parameter area in the FPGA, the power or reset from time to time in charge of monitoring software to load and initialize.

3.2.3 Reconstruction of the process of

Re-presentation of the structure verification system shown in Figure 4, when an error and failure, by the ARM processor to read Reconstruction of FLASH program memory. However, FLASH memory has a choice of many reconstruction program is subject to external 1553B, Spw, UART control. By the ARM processor to update or to complete the FLASH memory and / FPGA string conversion issue control commands to the application of reconfigurable modules to operate. JTAG port of FPGA simulation and the two FPGA's JTAG port the application of boundary scan chain (Boundary-Scan Chain), in under the control of ARM processor, reconfigurable FPGA to be reconstructed. FPGA's main task is to advance through the ARM controller logic into the FLASH system configuration information of the different functions, according to the user's system requirements and external control of timing, one by one to download to the SRAM of the FPGA programming, and system functions in order to achieve dynamic partial reconstruction. The course of their work in the system, FPGA will be in accordance with different requirements, under the control of the processor, and constantly remodeling its logic function, through the reconstruction of a template class, meet the needs of different digital image processing and other requirements of logic operations.

3.3 to achieve partial reconfigurable FPGA dynamic selection and configuration mode

3.3.1 Xilinx's Virtex-4 family of FPGA

In the choice of device, the device must ensure that resources have a certain margin, so that cabling can be avoided not only crowded, but also to facilitate the revision and extension testing. According to system needs and scalability, choice of Virtex-4 family of FPGA. It is a series of Xilinx Introduces Dynamic partial reconfiguration of the FPGA chips, is also based on the look-up table. Virtex-4 family of advanced silicon chip module combinations (ASMBL) architecture and features a wide range of flexible combination of greatly improved programmable logic design capabilities, thus becoming a powerful alternative to ASIC technology products. Virtex-4 choice of using Xilinx's Virtex-4 family of products XC4VSX55. XC4VSX55 with 128 × 48 line array, 55 296 logic cells, 24 576 Slice, the largest distributed RAM384 KB, 512 months XtremeDSPSlice), 320 months 18 KB block RAM, the largest block RAM storage capacity 5 760 KB, 8 months DCM, 4 months phase-matched clock divider (PMCD), 13 months I / O Group, the largest user I / O number 640. In accordance with existing algorithms, its performance and resources to better meet the image matching algorithms and object recognition algorithm to the hardware resources (logic gate count, RAM size, multiplication adder, etc.) needs. Virtex-4 hardware IP core blocks, including a huge array of PowerPC processors (with a new APU interface), three-state Ethernet MAC, 622 Mb / s to 6.5 Gb / s serial transceivers, dedicated dsp S1ice, high-speed clock management circuitry, and source-synchronous interface blocks.

3.3.2 Virtex-4 family of FPGA in the system configuration mode

Virtex-4 device is configured to use serial slave mode, serial master mode, SelectMAP from the model, SelectMAP main model, boundary-scan mode (JTAG) bit streams, one of the internal configuration memory load: in the system used in Reconfigurable FPGA application module configuration mode, there are two:

(1) JTAG mode (boundary-scan mode)

SPARTEN-3AN through FPGA series provides dedicated JTAG external logical drive with the same 4-pin JTAG pin FPGA and configuration of the two applications PRROM their series, the formation of boundary-scan chain (Boundary-Scan Chain) to download configuration data in the FPGA. In this mode, a TCK data to the speed of each load, as shown in Figure 5.

Based on Dynamic Reconfigurable FPGA System Design and Implementation

Picture not clear? Click here to view the image (larger).

JTAG or boundary scan mode is an industry standard (IEEE1149.1 or 1532) serial programming mode. The model through the cable, a microprocessor or other external devices to provide logical drive dedicated JTAG and JTAG test pins TCK clock input. Maintained at zero when the state of TCK, the test should remain the same logic state; TMS test mode for choice, control JTAG state. Appear in the TMS signal at the rising edge of TCK sample from the test logic into the test access port (Test AccessPort, TAP) controller; TDI: test data input, test data sample in the rising edge of TCK to enter the shift register (SR); TD0 : test data output, the test results in the falling edge of TCK from the shift register (SR) out, the output data and the data entered into the TDI does not appear to be inverted. This model because of its standardization and adoption of the same 4-pin JTAG for FPGA programming and extensive use of the capacity. JTAG approach commonly used in online programming (In-System Programma-ble, ISP), on the FPGA programming.

JTAG programming has also changed the characteristics of the traditional production processes, will be carried out prior to on-chip pre-programmed on-board re-installed to simplify the process for the first device to a circuit board fixed, and then port JTAG programming. Xilinx's Virtex-4 family support in a boundary-scan (JTAG) chain to configure multiple FPGA, each time, only the configuration in the chain of a FPGA, significantly reducing the degree of difficulty to achieve.

(2) PROM configuration mode is SPARTEN3AN series FPGA for each Virtex-4 family of FPGA configuration PROM the Line of Control a group of FPGA to achieve the download. SPARTEN3AN series FPGA and reconfigurable application of each unit virtex-4 family of FPGA, respectively, between a group of PROM control lines, each group includes DIN (data input configuration), CCLK (configuration clock), DONE (FP-GA configuration completed), PROG (trigger re-configuration), INT (initialization configuration) 5 signal, these signals through the configuration data will be downloaded to a Virtex-4 family of FPGA in to. Two methods complement each other in the boundary scan chain faults affect the entire chain of functions, you can use the PROM mode of replacement and improve the reliability of the reconstruction process.

4 Conclusion

The SRAM-based FPGA marked the advent of modern technology could be the beginning of reconstruction, and greatly promoted its development. Programmable FPGA algorithm can be designed according to different hardware structures to achieve the implementation of efficiency. Dynamically reconfigurable FPGA can run in the dynamic complete FPGA configuration circuit different functions in different times of the implementation of different algorithms, the realization of the virtual hardware reconfigurable computing technology. The adoption of this proposed increase FPGA microprocessor combination of serial daisy chain to achieve reconfigurable manner, the realization of reconfigurable FPGA dynamic structural design of an application. In addition, the verification system demonstrated reconfigurable controller can also be modular structure that can be used on other works of design, flexibility and portability advantages of strong.


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