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CPLD based on the parallel data collection and storage

Print View , by: iSee ,Total views: 14 ,Word Count: 1936 ,Date: Mon, 22 Jun 2009 Time: 11:23 PM


In the radar control and data acquisition system used in parallel data bus control signal transmission method and data exchange. In the past, the design of large-scale use of small and medium-sized integrated circuits and discrete components to build bus data acquisition and control module, the PCB is not only occupy a larger area, and the design of the workload and the complexity of timing control, acquisition speed is not ideal.

The CPLD is applied to the design of the system can effectively address the issue. CPLD can achieve many of the functions of small and medium-sized integrated circuit, the PCB can be effective in reducing the size of the functional modules, while reducing system size. CPLD using the online programming and simulation system can simulate all kinds of functions of the timing signal, greatly increased design efficiency.

l system hardware structure

In order to achieve high-speed data processing and data transmission, system bus interface CP-CI forms. The radar system design provided for two parallel data bus interface. Parallel all the way in which control by the CPLD, the storage system has been prepared in the data sent to the radar; another way to receive the radar echo signal returned by the CPLD control to put in storage. System block diagram shown in Figure 1.

CPLD based on the parallel data collection and storage

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1.1 CPCI bus interface

CPCI bus interface that takes care of the high-speed PCI bus, while discarding the Finger-style interconnection means, and switch to 2 mm pinhole density connector, improved system reliability, enhanced load capacity. In the industrial field has been widely used.

PLX bus interface circuit's high-performance interface chip PCI9054. It uses advanced data pipeline structure of PLX Technology, is a 32 b, 33 MHz of the PCI bus controller. Its main characteristics are as follows:

Support master / slave two visits, the peak transfer rate of up to 133 MB / s; provides two independent programmable DMA controller, support for each channel block and dispersion / concentration of DMA mode; Local Bus rate as high as 50 MHz, local bus clock can be provided by the external and the clock with: PCI clock synchronization; there are six kinds of programmable FIFO, in order to achieve zero-wait burst transmission and local bus and PCI: between the asynchronous bus operation.

System to start when configured in the system cycle, PCI9054 Configuration E2PROM read from the configuration information to complete initialization people. NS93CS56 here used to initialize the PCI9054 to complete the configuration.

1.2 Programmable Logic Device

ALTERA programmable logic device company selected EPlC3, its model range of products for the Cyclone, an internal logic analyzer functionality. In JTAG mode, by downloading the various cables can be observed in all IO pins and internal data registers, debugging is very convenient.

1.3 Memory

The system used in dual-port RAM as a PCI bus and parallel data storage and exchange medium. Taking into account the parallel exchange for a larger amount of data, so selection of IDT's 64K × 16 b dual-port chip IDT70V28. Ping-pong way into the storage structure in order to achieve the parallel operation, saving the processing time to ensure that real-time processing.

2 System Design and Principle

2.1 Phase-Locked Loop

PCB used in the crystal or crystal oscillator output frequency lower, and can not meet the system requirements, in order to receive a higher sampling rate, there must be a high-frequency clock as the system clock. EPlC3 internal phase-locked loop functions can be carried out on the input clock frequency and lower frequency of treatment, can also produce different clock phase. Frequency of the clock after the CPLD can be used as the internal use of the system clock can be output to an external CPLD, as the clock input of other devices.

In this system a 20 MHz crystal oscillator as the clock input of the CPLD through a 100 MHz frequency of the clock as the internal system clock, at the same time generate a clock output 33 HMz as asynchronous PCI9054 local bus clock.

2.2 Parallel Data Transceiver

Radar echo, including 16-bit width of the data and handshake signals, first of all need to shake hands with CPLD to receive and process signals. Received, to shake hands with the signal for falling edge trigger pulse. Note that the received signal must be removed to shake hands with glitches and noise arising from interference, to avoid the system to receive wrong data. In order to remove the burr interference impact should be low to maintain a certain period of time in order to reduce false triggering. Burr under the system set the cycle and noise detection threshold, for example, when the handshake signal transmission by cable to the interface board, sometimes in the forefront of a 15 ~ 20 ns of the burr, it can be detected after the falling edge handshake signals Then more than four consecutive record low-level signals of the clock cycle, only when the four cycles of the signal level to the "0" when it is determined to shake hands with this effectively. Schematic diagram of parallel port to receive data as shown in Figure 2.

CPLD based on the parallel data collection and storage

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The needs of the parallel output data from the memory after reading out the signal should be placed in the handshake on the output and to maintain, to be stable in order to parallel data output handshake signals. Handshake signal and the delay time to shake hands with the width of the signal can be set so as to enhance the adaptability of the system. Schematic diagram of parallel port to send data as shown in Figure 3.

2.3 Data storage and exchange of

The system by the dual-port RAM as the system input and output data buffer, by the CPLD and the common use of PCI9054 bus interface. Because a larger amount of data input and output, input and output operating frequency, it can be dual-port RAM of the storage space the same as the average degree of division of the growth of the two and a half years, half of the input and output data storage space occupied. When the CPLD to do the first to write a piece of data storage space, PCI9054 canfrom this storage space, but also be able to write another piece of data storage space, so that almost half of the operation to save time. But when the two ends of dual-port RAM with an address at the same time unit, respectively, read data and write data operation, the data read out is wrong. To prevent this error, you can use the dual-port RAM's internal arbitration mechanism to determine the use of BUSY signals. When an address to read the data in the unit first to determine whether the low signal BUSY, BUSY signal low if the said dual-port RAM is the other side of the address to write unit. Arbitration mechanism can be used to read and write effectively eliminate the conflict, but the system also needs to continue to dual-port RAM of the BUSY signal to judge. This will occupy a serious system resources, but also affect the data transmission speed. This system, the use of ping-pong structure will once again receive and send data all the storage space is divided into two parts of equal length. Schematic diagram of the final allocation of storage space shown in Figure 4.

CPLD based on the parallel data collection and storage

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Receive data, when the CPLD will be a space filled with the source data generated after the interrupt signal to the PCI9054 and information to produce a logo, PCI9054 interrupt signal received inquiries after the first signs of information to determine a storage area which has been written, and then the storage space and send the data read out system. CPLD can continue at this time to write another piece of data storage space. Similarly, when the PCI9054 to the area in which to write a piece of data sent, CPLD cananother area.

The form of ping-pong memory structure enables data exchange and data processing can be carried out in parallel, which greatly saves the processing time, the system requires real-time and its significance.

2.4 Interface Timing Control

When the radar echo data and dual-port RAM data ready at the same time Huai, the PCI9054 local bus as a result of faster read and write, if the first receive data, the dual-port RAM in the data may overflow, and if the first dual-port RAM in the data ready to send out the data need to wait to receive a certain period of time, affecting the real-time systems. CPLD must therefore control the read and write dual-port RAM timing, even if the data is not sent overflow area at the same time without affecting the system's real-time. As the dual-port data rate systems compared with the relatively slow speed, this system uses a time-sharing solution to deal with. First of all, to judge the validity of handshake signals, handshake signals if the parallel port is an effective indicates that receive data will be written into the dual-port RAM, otherwise the parallel port is in the reception time interval, CPLD on the dual-port RAM write operation does not. Because each parallel data transfer rate relatively fixed, so time can be unpredictable. In this interval will be dual-port RAM to read out the data and send it through this method can be further enhanced to send and receive data rate to reduce the data retention time of the double-mouth and more to improve the system's real-time.

3 Conclusion

In this paper, the previous single-chip CPLD needs to complete a large number of peripheral devices to complete the parallel port data of the radar transceiver and storage features, the CPLD design has been applied to radar systems, their application results show that:

(1) the use of CPLD greatly simplified the system architecture, reducing board size, lower system heat and interference to improve the reliability of the system, but also to debug a tremendous maintenance convenience.

(2) allows the use of Quartus Ⅱ hardware "software" of auto design, updated the traditional way of circuit design and debugging, greatly reducing the development cycle, especially its timing simulation and analysis of the design makes the design more reliable and to ensure the correctness of the logic of the system .

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