FPGA-based high-speed real-time data acquisition system design
With the rapid development of information technology, real-time data acquisition and processing in a modern industrial control and scientific research has become an indispensable part. In the signal measurement, image processing, audio signal processing such as high-speed, high-precision measurements of both the need for high-performance data collection.
Traditional data collection systems are often single-chip computer or digital signal processor (DSP) as a controller to control the analog / digital converter (ADC), memory and other peripheral circuits work. However, due to its single-chip instruction cycle and the effects of processing speed, and its relatively low clock frequency, the various functions of the run we have to rely on software to achieve, software running time in the entire sample period the proportion of large and less efficient , it is difficult to meet the system's data acquisition system and real-time synchronization requirements. However, DSP-based data acquisition system, although the processing speed, but the cost is higher, too frequently interrupted the CPU will reduce the efficiency and response speed variation.
The use of programmable logic device design data acquisition system with a short development cycle, integrated high-, low power consumption, high frequency, low-cost design, programming and other advantages of flexible configuration. In addition, FPGA chips can be carried out in the acquisition and control, buffering, processing, transmission control, communications. However, the use of FPGA as the controller data acquisition system, there are some problems, mainly a general rule, each plug-in data buffer to reduce the transmission speed of the system and increase costs. This paper presents a FPGA-based synchronous acquisition, real-time data collection to read the data acquisition program, increased the speed of acquisition and transmission system. FPGA as a controller of the data acquisition system, the completion of the main control channel selection, gain settings, A / D conversion control, asynchronous FIFO data buffer function of four parts.
l Selection of the main devices
1.1 Selection of the programmable gain amplifier
sensor output signal as a result of generally weak, in order to make use of A / D converter full-scale resolution, the sensor output needs to be a weak signal amplification, because the signal output for each channel in general different, so the provision of amplification for each channel multiples should be different. Optional programmable gain amplifier cascade PGA202/203 provided for each channel a different magnification. PGA202/203 is the gain of the single-chip digital control can be integrated amplifier, which for the PGA202 Gain Fan 1,10,100,1 000 (10 hexadecimal); PGA203 Gain Fan for 1,2,4,8 (binary). PGA202/203 cascade can be achieved using 1 ~ 8 000 16 different magnification, fully able to meet the different signals of different magnification and a wide range of signals and weak signal detection require the collection requirements.
1.2 A / D converter selection
A / D converter data acquisition system decision accuracy and resolution, so A / D converter selection is particularly important. Select A / D converter needs to be considered the main factor of resolution, accuracy, speed, power requirements, interfaces and the type of converter.
A result of successive approximation type A / D converter with fast conversion speed and high precision, flexible and affordable features, so consider accuracy, speed and cost, the selection of TI products selected specifically for the data acquisition system successive approximation type 16-bit A / D converter ADS8322. The main performance indicators are as follows: a resolution of 16; sampling rates up to 500 kHz; inside the baseline with 2.5 V source; unipolar input; inside with sample-and-hold device; low power consumption; in the sampling rate of 500 kHz when power consumption is 85 mw; 16-bit data output in parallel. ADS8322 minimum clock cycle for 100 ns; largest acquisition time of 0.4μs; maximum conversion time of 1.6μs; maximum data rate of 500 kHz. From performance indicators from the ADS8322 can be seen, ADS8322 is ideal for high-speed, high-precision data acquisition system.
1.3 FPGA chip select
FPGA is used to control the main co-ordination of the whole system. Data acquisition system as a controller, is responsible for control of A / D conversion work, channel selection, gain settings, as a data acquisition system, such as buffer memory. Integrated chip performance and cost considerations, selection of a new generation of low-cost A1tera company FPGA-Cyclone Ⅱ Series EP2C50F484 chips, Cyclone Ⅱ FPGA is based on the Stratix Ⅱ Technology 90 nm low-cost FPGA. Its based on the cyclone to increase the hard dsp blocks, the largest-scale Cyclone Ⅱ is Cyclone's 3 times the overall performance of the chip is superior to Cyclone series of devices. EP2C50F484 chip with 50,528 logic cells, 86 embedded 18 × 18 multiplier modules, four phase-locked loop, 129. M4K RAM, 4 clock control block, the 16 global clock networks, the total RAM space 594 of the 432, the largest user of available I / O pin number of 294. Cyclone Ⅱ made suitable for the complexity of the logic and storage, the buffer function of data acquisition system.
2 the overall structure of the system
Overall system block diagram shown in Figure 1.
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The entire system by the signal conditioning, acquisition conversion, timing and logic control, buffer storage, and high-speed data transfer interface, such as parts. Signal conditioning circuits include signal amplification and signal filtering circuit, because the sensor output signal is typically weak, in order to take full advantage of A / D converter full-scale resolution, on the need to enlarge the input signal. Because of different input signals in general require different magnification, so selection of signal amplification to complete the programmable gain amplifier. Programmable gain amplifier gain control from the FPGA programming; signal filtering in accordance with the requirements of the Shannon theorem. Taking into account A / D conversion rate, the bandwidth of the input signal to limit the sampling signal generator in order to prevent "aliasing phenomenon"; acquisition conversion is completed ADS8322 analog signal conversion chip digital; timing and logic as well as the buffer memory by the FPGA to complete. FPGA is mainly responsible for the choice of channel acquisition, programmable gain control of magnification, A / D converter control, data collection tasks such as buffer storage. Selection of high-speed data transfer bus USB bus, uSB bus plug and play. agreement uSB 2.0, data transfer rate up to 480 Mb / s, which is entirely possible to meet the high-speed data acquisition and transmission requirements.
Verilog-based design of automatic data acquisition system controlled by the hardware A / D converter and automatic FIFO memory to store data. Sampling frequency clock output from the FPGA decision, when the data in the FIFO when full, FIFO full marks (FULL) Purchase 1, data transmission through the USB bus to the computer store, pending follow-up. As the first data into the FIFO to the output, so collection will not be interrupted, so that it can achieve continuous real-time data acquisition and real-time data processing.
3 Simulation results
3.1-channel selection and magnification settings
8-channel selection to choose from a data selector to complete, through the input signal b [2:0] to choose different combinations of different channel (Charmel); through the cascade PGA202/203, magnification in the control of PGA202/PGA203 client a3a2 / a1a0 when different combinations, different magnification settings. For example, in the a3a2 a1 a0 = 0000, set the gain of gain of 1; in the a3 a2 al a0 = 0001, set the gain of gain of 2; in ... a3a2al a0 = 11ll when the gain setting for the 8,000 gain. Gain gain from the l ~ 8 000 settings, such as the waveform shown in Figure 2. Gain a wide range of settings can be realized on a wide range of signal detection as well as the weak signal acquisition. Modelsim SE 6.1b in software for the FPGA control of channel selection and gain settings of the simulation, the simulation waveform shown in Figure 2.
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3.2 FPGA design to control the conversion ADS8322
According to the work of conversion ADS8322 timing diagram, the FPGA control VerilogHDL prepared ADS8322 conversion process. In Quartus Ⅱ 7.2 in the compiler software synthesis; ModelsimSE 6.1b in the form of a simulation, the simulation waveform is shown in figure 3. As can be seen from the simulation waveform, and its work in full compliance with the timing of the ADS8322.
3.3 Design of storage and transmission module
FPGA internal self-594 432-bit data RAM as a buffer, so that can take full advantage of FPGA resources, improve system speed and system cost savings, EP2C50F484 chip largest available I / O pin count of 294, with Verilog language EP2C50F484 interior design in an asynchronous FIFO (first-in-first out memory). When in the design of asynchronous FIFO, it is not possible only to set up a FIFO counters to record the changes in the remaining space as it is impossible to allow two different control with a variable clock. Therefore, indicators must be compared to determine the read and write FIFO is empty, is full, or in other status. As state and full state space, the read pointer and write pointer are the same, so take an increase in each indicator bit to a bit the difference between empty and full state of the state of the method. If the write pointer increments to the end of the FIFO beyond the address, the new 1-bit digital to change the times, reading the same pointer. Thus, if the maximum on the two different indicators, it said in a FIFO full state; exactly the same as if the two indicators, this indicates that the state is empty.
3.3.1 FIFO Design Guidelines
If the FIFO pointer count increase or decrease in the use of binary mode or lower in the counter 1, there may be a bit more than a change in place (such as 1011 ~ 1100), the clock in a number of changes along the synchronization signal comparison difficulties. Based on this problem, the use of Gray-code counting method to change the pointer in each conversion clock change only one bit pointer bit.
3.3.2 FIFO software program
FIFO by the software program composed of five modules, namely, top-level module (fifo), memory modules (fifomem), time synchronization module pointer (sync_r), write pointer synchronization module (sync_w) and space module to determine the status (r_empty), full determine the module status (w_full). Each module are vetilog language programming, in the Quartus Ⅱ 7.2 in the completion of the compiler and synthesis, and ModelSim SE 6.1b for waveform simulation. Simulation waveform storage module shown in Figure 4, the waveform can be seen that the first data into the memory (wdata) first output; time address (radder) and write the address (wadder) the same can also be different. Waveform can be seen from the simulation, the FIFO design to achieve the desired function.
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To achieve high-speed FPGA-based real-time data acquisition system design. The use of FPGA data acquisition system as the core of the control through the software programming to control the choice of hardware channels; through a programmable gain amplifier to achieve the magnification control; use FPGA to control the realization of A / D conversion, and gives control of the conversion wave. This shows that the control waveform conversion in full compliance with the timing of the ADS8322, is designed to achieve. Own use of RAM within the FPGA to design a 16-bit FIFO, the buffer can be data storage, full use of system resources, system cost savings, with good portability and scalability, easy to debug and modify. In addition, based on first-in-first out memory (FIFO), first-out characteristics of their ancestors, can achieve high-speed real-time data acquisition. In high-speed real-time data acquisition have better application prospects.
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