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FPGA-based signal source to generate the multi-functional system design and implementation of

Print View , by: iSee ,Total views: 16 ,Word Count: 2130 ,Date: Tue, 23 Jun 2009 Time: 11:23 PM

Product-level signal sources are often unable to meet the needs of scientific research and experiment, especially in a complex electromagnetic environment of research and experimentation, it is necessary to signal a variety of styles, and in accordance with the different scenes, the need for signal patterns, the number of changes have taken place.

Field Programmable Logic Array (FPGA) in ASIC inherited the large-scale, high integration, high reliability, the advantages and overcome the general ASIC design cycle length, high investment, the flexibility of the shortcomings of poor, and gradually become a complex digital hardware circuit the ideal choice for design. In order to meet the needs of scientific research and experiments, the need to produce a series of signals, in order to design an FPGA and high-speed D / A as the core. Center frequency can be 30 ~ 130 MHz in the various parameters can be adjusted radar, communications, navigation and multi-purpose noise source signal generation system.

1 system hardware structure

Signal source to generate multi-functional system in the integrated controller under the control of one or more of the center frequency of 30 ~ 130 MHz in radar, communications, navigation, noise and other signal output Ping 60 ~ o dBm. Step value of 0.06 dB. System is mainly by the integrated controller, signal generator, rf antenna modules and four parts, as shown in Figure 1. Integrated controller to achieve the overall control system, including the signal approach and the various signal parameters. Signal generator control parameters include interface conversion module and the signal generation module in two parts. RF module to complete the two main functions, namely, 650 MHz clock generation and IF input signal frequency, the final output signal by the antenna.

2 integrated controller

Integrated controller for a single industrial computer, complete control of the main parameters of the input and the digital base-band signal generation. Control through an integrated controller interface input control parameters, these control parameters through the computer interface into uSB signal generator, to achieve the control signal generator. Digital base-band signal is a certain flow rate of the binary code in the controller to complete the system will be integrated into a certain BMP picture of the binary data rate and input through the USB interface to the signal generator, as a system of digital baseband signal . Integrated controller in the work, to the signal generator into the control parameters, such as the signals approach and the various signal parameters (signal pattern, operating frequency, power output, modulation index, the delay time, frequency-hopping rate, pulse width, pulse cycle etc.), when the control parameter input after the beginning of the use of an integrated USB controller interface transfer images from BMP binary data conversion. System in the course of their work can change the control parameters in real time and follow the instructions to set, when the digital baseband signal transmission will be suspended, waiting to continue output after update.

FPGA-based signal source to generate the multi-functional system design and implementation of

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3 Signal Generator

Signal generator consists of two parts, namely, the conversion interface module control parameters and signal generation module. Interface Converter Module control parameters to complete the integrated USB controller through the control of transmission line parameters of transmission and digital base-band signal is converted to the data bus into the bus, the signal generated by the module control parameters have a specific signal.

3.1 Control Parameters Interface Converter Module

Control parameters interface converter module from USB interface to receive the data received, and to receive data into a data bus into the backplane bus. Conversion interface module control parameters include two parts: USB control chip and an FPGA, as shown in Figure 2. In this module to complete the data packet access and split the two operations. Packet access is the USB controller chip USB transmission line will be one of the 16-bit data is converted to the FD signal to the FPGA in. FPGA and then receive data packets in accordance with the Resolution of the agreement is divided into 16 control parameters 160 kHz signal DATA and the digital baseband signal to the backplane bus DATAl60K At the same time, transmission through the bus clock signal and two AIOW and CLKl60K. AIOW which is the signal DATA and the control parameters to match the clock, is sent by the FPGA bus, and is CLKl60K digital baseband signal to match the DATAl60K clock signal generator from the bus into the FPGA through the . Packet by a split Spartan3 FPGA (XC3S200) to realize.

FPGA-based signal source to generate the multi-functional system design and implementation of

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3.2 Signal generation module

Signal generation and high-speed FPGA module to take D / A method of combining, in the FPGA high-speed sampling data generated internally. Give high-speed data sampling D / A signal to restore. In this system, FPGA chip companies selected Xilinx's Virtex-4 series XC4VLXl00, and high-speed D / A choice of AD's AD9736. As shown in Figure 1, the signal generation module includes two signal generation circuit boards, each board has two FPGA and four high-speed D / A, each FPGA and two D / A connected, that is, within an FPGA need to have a 2-way signal at the same time sampling data, the entire system can generate signals 8.

FPGA clock is the work of RF modules in high-speed clock generated by D / A with the completion of the second sub-frequency to the FPGA after the. Because each FPGA and two D / A connected, so it also has two input clock. Clock and data in order to maintain the homologous characteristics of the internal circuit in the FPGA design has adopted a concurrent design approach, that is, to the high-speed D / A sampling of high-speed data with the matching clock is sent by the clock to generate and and with another D / A into the clock has nothing to do, and maintained the independence between the various signals. At the same time, the RF module can generate coherent and non-coherent clock, allowing the system to produce coherent and non-coherent signal. In addition, into the D / A external clock can also be sent, greatly increasing the flexibility of the system.

FPGA internal modular design approach taken, including the parameters of the distribution module, a variety of signal sampling data generation module and the signal for sampling data signals to generate a variety of modules and signal summation module, its design diagram shown in figure 3. The main parameters of the distribution module to receive the various bus signals DATA signal control parameters assigned to each signal sample data generation module, its internal control diagram shown in Figure 4. Parameters of the distribution module AIOW the rising edge of clock time, in accordance with the control parameters of the high signal DATA, the identification of 15 low-DATA is the data for the address, if sent to the address for the address latch latches; If the data is sent to the address decoder from the address decoder to determine the agreement in accordance with decoding data for a particular signal sample data generation module specific control parameters. Signal sample data generation module is based on the parameters of the distribution of sampling data to generate the necessary signal to the summation module. In order to reduce the sum of signal energy module brings the loss of signal, the design is not the traditional way of interception of a high output, but the interception to take a low output mode, which ensures that there is no summation in the case of overflow, system to maintain the specified output parameters without loss of signal energy. Summation in order to prevent overflow, resulting in signal distortion, in an integrated controller and do the processing, the control input of control parameters in the appropriate range.

FPGA-based signal source to generate the multi-functional system design and implementation of

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Signal sample data generation module can be generated in this mode of combination of one or more signals, but also necessary. Through the input control parameters, real-time change the mode of combination. Figure 3 indicated that only a combination of the relationship between modules, if under such a combination can not meet the needs of experiments and scientific research, the system can be re-programmed software, download to FPGA, thus the required sampling.

About 4 AD9736

AD9736 is AD Company. 14 b produced a high-speed DAC, the sample clock rate broke through the 1 GSPS, reached 1.2 GSPS, and extremely low power consumption. AD9736 output current in the range of 10 ~ 30 mA with programmable and very easy to configure single-ended or differential output circuit. AD9736 using LVDS data interface, can effectively ensure high-speed data transmission. Twice as much internal support AD9736 interpolation, and embedded in a 55-order symmetric FIR interpolation filter, the filter passband flatness to within O. 001 dB, stopband attenuation reached 90 dB, the transitional zone of 20% ~ 30%, thereby greatly reducing the speed of sampling data. [2] lists the AD9736 in the 800 MSPS, 1 GSPS and 1.2 GSPS sampling rate of spurious-free dynamic range (SFDR) and intermodulation distortion (IMD), the Figure 5, shown in Figure 6. The device at 1.2 GSPS sampling rate, 255 MHz output frequency intermodulation distortion (IMD) is 74 dBc, and output in the 600 MHz frequency IMD is better than 60 dBc, sFDR in the 300 MHz output frequency at 62 dBc.

FPGA-based signal source to generate the multi-functional system design and implementation of

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5 System Performance

The real-time signal generation system to produce single or multiple center frequency 30 ~ 130 MHz in a variety of signals, such as tone, AM, PM, FM, ASK, FSK, BPSK, QPSK, Frequency Hopping, Direct Sequence Spread Spectrum, white noise and so on, also can simulate a variety of radar transmit pulse and echo signals. In addition, the ISE can also download and re-programming the FPGA to achieve more complex signal.

Signal generated by the system in the frequency, magnitude and achieve a variety of other adjustable parameters, the frequency resolution of 0.35 Hz, output level for -60 ~ O dBm, step value of 0.06 dB when, SFDR better at 60 dB. At the same time as the system can launch multi-channel signal, and a number of antennas, which can be used to simulate firing from different directions on the complexity of multi-channel analog signal electromagnetic environment. Similarly, the system also can be used as sources of interference and signal sources for a variety of interference and interference study of the test. Figures 7 and 8, respectively, for the system to produce the FSK signal waveform and frequency spectrum; in figures 9 and 10, respectively, for the system simulation of FSK signals transmitted through multipath waveform and frequency spectrum.

FPGA-based signal source to generate the multi-functional system design and implementation of

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6 Conclusion

The use of FPGA and high-speed D / A combination of the realization of the signal source, simple structure, flexible control, superior performance, but also necessary in this platform to re-download to the FPGA, the changes in its internal circuit, rather than the other system board, This will not only save time and reduce costs, but also conducive to the improvement of the signal source. In addition, the system also can be used as base-band signal unit, mixer circuit in any combination required to achieve a variety of styles-band signal.


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