HDMI Design Guide: HDTV receiver applications, the success of high-speed PCB design
Multiplexer for use HDMI repeater users, this article provides a how to design printed circuit board (PCB) to achieve optimal device performance of all the design guidelines. We will high-speed PCB design some of the key aspects of the interpretation of important concepts, and gives some suggestions. This article covers a layer stack, stitch differential, controlled impedance transmission lines, non-continuity, wiring guide, reference plane, through-hole, as well as the content of decoupling capacitors.
HDMI Multiplexers pin outer repeater is designed for HDTV receiver circuit design (see Figure 1) and tailored. Package provided to each side of a HDMI port, has four differential TMDS signal in order to achieve the three input ports and one output port. The remaining signal from the power supply rails, Vcc and ground as well as the low-speed signals (for example: I2C interface, hot-swappable and selector pin multiplexing) components.
Completed the design of a low-EMI PCB stack requires a minimum of four (see Figure 2). Layer stack should be in accordance with the following order (from top to bottom): TMDS signal layer, wiring layer, the power level and control signal layer.
Figure 2 the proposed receivers in a PCB design using 4 or 6 layer stack.
On the top floor of high-speed TMDS lines to avoid the use of trace wiring through-hole (and inductance), and allow the connector from the HDMI input to the repeater and the repeater output from the receiver circuit to follow-up to clean the Internet (clean interconnect).
In the high-speed signal layer below the ground to place a solid layer, so that the transmission line will be the establishment of a controlled impedance interconnect, and provide an excellent return to the current low-inductance path.
In the next layer below the ground level to place the power to create additional high-frequency bypass capacitor.
Wiring in the bottom of the achievement of low-speed control signal can be greater flexibility, because they usually have a signal chain to allow non-continuous (such as through-hole) of the margin.
If you need an additional power supply voltage level or signal level, then it should add a second layer power / ground layer to the stack system in order to maintain symmetry. This allows the stack to maintain mechanical stability, and to prevent its deformation. Power of each power system grounding layer and layer can be placed closer together, thus substantially increasing the high-frequency bypass capacitor.
Differential trace line
HDMI converter to minimize the use of differential signaling (TMDS), for high-speed serial data transmission. Differential signaling for the single-ended signaling brought about tremendous benefits.
In single-ended system, the current through an inductive load from the power flow to and through a ground layer or line return. The horizontal currents caused by electromagnetic (TEM) wave will be free of radiation to the external environment, thus giving rise to serious electromagnetic interference (EMI) (see Figure 3). Moreover, the inductance of the external source of noise is inevitable that the receiver was amplified, in order to break the signal integrity.
Differential signaling to be used to replace the two inductors, one for positive current and one for the current return. Therefore, when the close-coupled, the two inductors of the current contour, but the polarity is opposite, and the disappearance of the electromagnetic field. Now, the electromagnetic field has been "robbed" of the two inductors are not TEM wave radiation to the environment. Only in the inductive loop of the edge of a very small external magnetic field will occur when the radiation, resulting in low EMI (see Figure 3).
Figure 3 from a single inductor large scattering around the magnetic field and differential signal loop inductance of the tight coupling of the external magnetic field of small scattering of TEM-wave radiation
Another closely-coupled the benefits of electricity, the two inductive sensors to external noise are equivalent forms of common-mode noise in the receiver input. The receiver has a differential input signal differences are only sensitive, but not sensitive to common mode signals. Therefore, the receiver of the common-mode noise suppression, and to maintain the signal integrity.
In order to enable differential signaling can work in a PCB, a differential signal on the distance between the two lines must trace the entire length of the stitch line. Otherwise, the pitch will change the imbalance caused by the magnetic field coupling, thereby reducing the elimination of the effect of the magnetic field, resulting in increased EMI.
In addition to more than EMI, the inductor can also lead to changes in spacing of the differential signal changes in impedance, resulting in impedance control of the interruption of transmission systems, signal integrity to damage the signal reflection.
In addition to the same pitch, the two inductors are required for the equivalent electrical length, to ensure that their signals reach the receiver at the same time input. Figure 4 shows the lines of different lengths equal to and tracks the logic state of a differential change in the period of the "+" and "" "signal.
Fig.4 Electric stitch length will cause the phase shift between signal and thus cause serious EMI issues arising from the differential signal
The same stitch length, the two signals equal and opposite polarity. As such, they and must be zero. If these electrical trace lines of different length, then the more short-term signals on the track will be more long-term signals on the track to change the status of earlier. In the meantime, the two lines are driven current trace to the same direction. Often as a result of the long-term as a return path to continue to drive current trace ( "early" drive current), so their short-term must be found through the trace of a reference layer (power supply layer or grounding layer) of the return path.
When the sum of the two signals, the total signal during the transition phase from the zero level during the transfer. In the high-frequency conditions, these differential signal to substantially the form of a sharp transient, and its displayed on the ground floor, thereby causing serious EMI issues.
Note that "noise" pulse width of the two signals with the phase shift between the same and can be converted to the frequency of a given time difference. The time difference (also known as the internal time-delay) from HDMI provides for 225 MHz TMDS clock rate of 0.4 TBIT receiver, will be converted to its maximum 178 ps. For a HDMI transmitter, the specification 0.15 TBIT, to 225 MHz for the TMDS clock rate, which will be converted to 66 ps max.
Pixels generated as a result of the needs of the four differential TMDS signal pairs (three data signals +1 clock signal) synchronous transmission, so the need to reach the receiver at the same time. Ideally, all four signals should be equal to the electrical length, to ensure that the time difference of zero. However, a 0.2 TCHARACTER + 1.78 ns in terms of the receiver, HDMI allows a maximum delay of the inter-(between the signal of the time difference), which will have a total time of 2.67 ns for 225 MHz clock of the TMDS . To a HDMI transmitter, the specification of 888ps have a 0.2 TCHARACTER.
Controlled impedance transmission line
Controlled impedance line trace transmission medium can be used to match the differential impedance (eg: cable) and the termination resistor. Differential impedance signal on the line traces from the physical geometry, which with the adjacent ground level, as well as the relationship between the dielectric PCB decision. These geometric shapes in the entire line must maintain a consistent track length.
Figure 5 describes the microwave transmission belt (Microtrip) stitch (stitch outer) and stripline trace lines (usually two ground floor was caught in the middle of the floor inside the stack trace) calculated impedance parameters.
Figure 5 Differential Geometry physical stitch
Figure 5 in order to calculate the impedance of 100Ω differential TMDS signal lines on the track geometry, you can use the closed equation 1 "6.
1, for the case of loosely coupled stripline, s> 12 mils, the number 0.748 to replace may be 0.374.
2, W <2h, the maximum error of 3%
3, in order to get the best accuracy, so that b "t> 2W and b> 4t, which, b for the ground between the dielectric layer thickness.
Taking into account the differential signal on the distance between and its environment, Figure 5 shows a line trace X, its not with the adjacent "+" and "" "a conductor of current relevance. X can trace a signal on line , a ground trace or shield a TTL / CMOS stitch.
For the neighboring signal lines and shielding on the track is concerned, so that the distance d equal to 3 s. Run in the side stitch shielding (grounding more appropriate), may create an increase in the imbalance of EMI. Grounding shield line should trace the lower ground floor there is a through-hole scattering.
Please note! At first glance the above equation, the show traces a line geometry will be less expensive method. However, these functions are based on empirical data, and on behalf of the approximation of the best of circumstances. The actual accuracy may be very different, for various reasons even as high as 10% of the possible error.
In the long run, a more accurate, lower cost approach is to use a 2D or a better field solver. It is a can of Maxwell (Maxwell) and calculate the equation for solving arbitrary cross-section of transmission line electric and magnetic fields of software tools. It can also be calculated from the above electrical performance of these items, such as: characteristic impedance, signal speed, crosstalk and differential impedance. Some field solver can also calculate the derivative of the current distribution of the body. Compared with the approximation, a 2D field solver to consider the advantages in almost all of its cross-sectional geometry of arbitrary flexibility. In addition to the first-order item (for example: line width, dielectric thickness and dielectric constant electrolysis), the second-order item (for example: trace line thickness, solder and etching back of stitch) can be taken into account.
Non-continuity of the signal path is differential trace impedance values deviate from its provisions (100Ω, that is, 15% HDMI), and to assume that a higher or lower impedance values. Non-continuity can be caused by impedance mismatch caused by signal reflection, signal integrity to damage. These are mainly the effective width or stitch line spacing changes between the results, which in turn changes the inevitable stitch along the signal path geometry transmission, or by poor signal line caused by trace routing.
Possible locations of non-continuity:
HDMI connector signal line with the track pad to meet Department
The signal encounter through-hole stitch, resistors, or IC pin component disk Department
Signal 90o bend stitch
Signal to be separated from an object to focus on the local Routing
In the differential impedance, TDR, and testing will detect the non-continuity. A TDR (Time Domain Reflectometer) is used to describe and position of a metal conductor in the failure of electronic equipment.
Conductor transmission along a TDR a fast pulse rise time. If the conductor is uniform impedance, and correctly terminated (terminated), then the whole pulse will be fired by remote terminal absorption, and no signal will be reflected back TDR. However, the existence of non-continuity of impedance, all non-continuity will be reflected back to form a reflectometer (reflectometer) echo. Impedance increase would have an enhanced echo the original pulse at the same time, reducing the impedance will have a relative with the original pulse echo.
In the output / input measure generated by TDR pulse reflection, which will be a function of time or the rendering of form, because a given transmission medium speed of signal propagation in relatively constant, and can trace the length of time the form of function out.
Figure 6 TDR display shows the location of non-continuity
PCB design is aimed at as much as possible to minimize the non-continuity, in order to eliminate reflection and maintain signal integrity. Follow a set of routing guides, help to avoid unnecessary non-continuity. The remaining unavoidable together should focus on non-continuous, that is the size of this region should be kept small and placed close as possible. The idea is to focus on the various reflex points in a regional, rather than their distribution in the entire signal path.
The use of TDR to see the continuity of the large number of non-directly affected by TDR using the edge of the pulse rate. TDR edge of the faster rate, there will be non-continuity of the more and the greater the impedance peak. Through the HDMI specification defines the edge of their speed (typically 200ps). Figure 6 for a description of the point. Map using the low line pressure 30ps edge rates, the use of high-line pressure filter 200pf. 200ps edge rate when using the filter when the pressure in the lower line of the TPA produced by SMA board are totally non-continuity can be seen.
When I try to maintain the signal integrity and low EMI, the PCB wiring has a number of guidelines is essential. Although it seems that there are numerous preventive measures can be used, but only recommend the use of this section the layout of some of the main guide.
1, does not match the point in the adoption of amendments to a small curvature to reduce the time-delay differential at home.
2, reducing the amount of components and IC placed outside the lead foot, as well as the larger perspective of the signal path caused by amendments to the inter-time-delay. The use of oblique bending type (chamfered corner), its length and width ratio of 3 to 5. Bending the distance between the line width should be at least 8-10 times.
3, using the 45 o bend (oblique-type bending) for right-angle (90o) bending. Bent at right angles will increase the effective linewidth, change the differential trace impedance, and thus give rise to a shorter break. A 45o bending can be seen as short a time breakpoints.
4, when an object around in the wiring, the response to a pair of parallel lines to wiring trace. Will be separated from the trace line will change the routing line and the spacing between lines, thus giving rise to differential changes in impedance, as well as the emergence of the phenomenon of non-continuous.
Figure 8 objects around in a routing
5, in the signal path within one after another to put some passive components, such as: the source of matching resistor or ac coupling capacitor. And case b) compared to case a) does give rise to the routing of the line of the wider track spacing, however, the resulting non-continuity of the phenomenon was limited to a shorter length of the electrical.
Figure 9 a variety of non-continuity
6, when a through-hole in the surrounding, or a row of through-hole wiring between the time to ensure that the through-hole gap there is no obstruction of the ground layer on the bottom of the current loop.
Figure 10 through-hole to avoid gaps
7, in order to better impedance matching, in the HDMI connector pad below, or between the pad to avoid the use of metal layer or stitch. Otherwise may lead to the following differential impedance to 75Ω, and burned during the TDR test your circuit boards.
Figure 11 the edge of each layer and to maintain a certain distance between the pointer
8, the smallest size, as far as possible the use of signal lines through-hole pad and HDMI connector, because of its differential impedance of 100 smaller impact. Larger through-hole and the pad may cause the following impedance to 85Ω.
9, the use of a solid grounding of the power layer and layer to achieve the 100Ω impedance control, as well as to minimize power supply noise.
10, the differential impedance of 100, it should be used as far as possible, the smallest interval stitch, your PCB manufacturers usually make their provisions. To ensure that the geometry of Figure 5 for the: s <h, s <W, W <2h and d> 2s. Can use a 2D field solver to determine a more precise geometry stitch all the better.
11, as far as possible, so that the HDMI connector and the electrical length between devices to maintain the shortest, so that a minimum of attenuation.
12, the use of better HDMI connector, the impedance in line with the specifications.
13, in close proximity, such as voltage regulator, or to provide electricity for the PCB, such as the Regional Office to place a large power supply capacitors (such as 10 ¼ F).
14, devices placed in the 0.1 ¼ F, or 0.01 ¼ F capacitor smaller.
Power high-speed PCB design layer and ground layer generally must meet the requirements. DC and low frequency in the cases, these layers must be integrated and end-termination resistor to provide stable voltage, such as Vcc and ground voltage.
High-frequency circuits for the reference layer, in particular, ground floor, there is a need to meet more requirements. Controlled Impedance on the design of transmission systems, the ground layer should be able to achieve with a layer of differential signal lines near the traces of electrical coupling. As previously mentioned, the close-coupled magnetic field will disappear, and thus has been reduced through the remainder of the TEM wave scattering radiation to minimize EMI. In order to achieve close coupling, should be a high-speed signal layer near the ground floor spaces.
Figure 12 microwave transmission band structure of the field coupling
Although the theory of differential signal transmission does not require a separate current loop, but there will always be a form of common-mode noise current and recent reference layer (in theory generally refers to ground level) in capacitive coupling.
For these currents to provide a continuous low-impedance circuit requirements for a solid reference to the copper layer, compact without cracks.
Power system with multiple layers of the stack can benefit from through-hole formed by the reference layer. Here at different levels of the ground floor through a large number of through-hole connected to these through-hole placed equidistant intervals in the entire circuit board. Similar connection also applies to the power layer.
Reference level for the connection, it is a very important point, that is, through-hole space (or ground through-hole in case of anti-pad) does not interfere with the current loop. Obstacles in the circumstances, the return current will find a channel to bypass the obstruction. However, if this is the case, the electromagnetic current will be very likely to interfere with the appearance of crosstalk of the other signal trace. In addition, the barrier will line the track, through its negative impact on impedance.
Figure 13 and trough dense ground layer of the current loop
Through-hole of the term generally refers to the electroplating of printed circuit board hole. A number of applications through the through-hole wide enough so that they could put the wire hole components, and high-speed circuit board design is generally carried out in the signal level changes as the use of through-hole stitch, or use as a through-hole connection to be required for SMT components and connected to a reference layer, but also a reference to the same potential connected layer (see the previous chapter mentioned in section connecting through-hole grounding layer).
With a through-hole to connect the various layers with a through-hole around the pad (through-hole pad) directly connected. Do not have to connect the various layers of the ring by a gap to open between and through-hole. Each through-hole and have a capacitance between grounding, power capacity can be used to calculate the following approximate formula:
Which, D2 = ground floor space of the hole diameter (diameter)
D1 = through-hole around the pad diameter (diameter)
T = the thickness of the printed circuit board (in thick)
dielectric constant ε1 = circuit board
Through-hole c = parasitic capacitance (pF)
Capacitance and size as a result of a certain proportion of the increase, therefore, the design of high-speed through-hole stitch should be small, so as to avoid large capacitive load caused by signal attenuation.
When a decoupling capacitor connected to the grounding layer, or to connect the various ground layers when compared with the capacitance, inductance through-hole is even more important. About the value of the inductor is:
Which, L = through-hole inductance (nH)
h = length of through-hole (with L)
d = hole diameter (diameter)
Since the equation involves a few, so to change the diameter of through-hole will not have any effect on inductance. Changes in the length of through-hole, or more through-hole parallel may make large changes in inductance. Therefore, each device should be placed two of the terminal through-hole parallel to the coupling capacitors and grounding connections. The ground floor of a low inductance connection between, the board should be to place the same number of through-hole interval.
Despite the strong line is not recommended for high-speed circuit trace layer change, but if it is necessary to change the case, should ensure that there is a continuous loop of current. The left part of Figure 14 shows the change for a single circuit layer of the current flows back to the right part of the circuit for a number of changes to the current layer back to the flow.
Figure 14 and more than a single layer circuit loop current changes
Central internal space-chip realization of a layer of metal layer formation from the bottom of the dock to the top of the current flow changes. Therefore, when a signal through a through-hole, and extended to the other side of the same level when there is no current back to the issue of non-continuity. Through a number of cross-reference from one layer to another layer signal trace layer change, so that the design of current loop so that complicated. Ground level in two cases, a grounding to the grounding of the through-hole must be placed in the vicinity of the signal through-hole to ensure that a continuous current loop (see Figure 14, the right side of the chart). If the reference level for different voltage potentials, as shown in Figure 15, the power layer and ground layer, the design of current loop will be more messy, which is due to the need for a third through-hole and a decoupling capacitor. Current signal back to the beginning of its current power supply closest to the bottom layer. After flowing through the power-off hole, the flow through the decoupling capacitor grounding through-hole, and finally back to ground level at the top.
Figure 15 and more than a single layer circuit loop current changes
There are a number of through-hole to place decoupling capacitors and the current loop has a high inductance, it is not conducive to signal integrity, and to increase the EMI. If possible, when carrying out high-speed cabling to avoid changes in the various layers, it is because it would reduce the performance of circuit boards to design complexity and increase of production costs.
Decoupling capacitors for the charge IC to provide some resources, the IC in response to the internal switch requires a large amount of supply current. Less than the amount of decoupling would lead to lack of supply current required to prevent the normal operation of IC, resulting in signal integrity data errors from occurring. This requires in the relevant frequency range to provide a low impedance. In order to achieve this objective, the usual practice is evenly distributed in a group of circuit board decoupling capacitors. In addition to maintaining the integrity of the signal, the decoupling capacitors EMC also act as a filter to prevent high-frequency rf signal is spread on the entire PCB.
When the power layer and ground layer connection between a capacitor, we actually have a configuration in the series resonant circuit to the power load, the frequency of the circuit depends on the capacitor represents the equivalent circuit of a real component of the RLC . Figure 16 shows an initial parasitic equivalent circuit components, as well as its series resonant circuit to a conversion.
Figure 16 Simulation of a series resonant circuit of capacitor loss
RL said that low-frequency leakage resistance leakage current circumstances of the loss. RD and CD that due to molecular polarizability (RD) and dielectric absorption (CD) loss arising. RS said conductors and capacitors in the resistance of metal plates. Three resistors to form a loss equivalent series resistance (ESR). In this case ESR, equivalent series inductance (ESL) for the metal plate capacitor and the inductance of the internal wires and.
Please note that although the connection through-hole capacitors low impedance, but will have a large number of series inductance. Therefore, we should end the use of capacitors in each of the two through-hole to reduce the through-hole inductors.
Figure 17 shows the capacitor impedance (Z) series with a 10 nF capacitor frequency. In much lower than the self-resonant frequency (SRF) under the conditions of dominant capacitive reactance. More closely with the SRF, the inductive reactance and capacitance by the attempt of the impact of weight. In the SRF, the capacitive and inductive reactance disappear, only the existence of ESR. Please note, ESR depends on the frequency, and with the usual belief, the SRF will not reach its minimum value, but the impedance Z will do.
Figure 17 capacitor impedance with frequency
Capacitors in parallel in a distributed decoupling network operation, because the total capacitance to the selected value decoupling capacitor N. And when the power capacity of this value, the capacitor impedance and as a result of the frequency has decreased below the SRF. Similarly, the inductance will change, this is because the frequency is higher than in the SRF when the impedance will be reduced.
Coupled to a reliable network design must include the lower frequencies as low as DC, and the need for large DC capacitor. Therefore, in order to provide adequate low-frequency low-impedance volume should be in the regulator output, as well as to provide power supply PCB to put in place 1 ¼ F to 10 ¼ F tantalum capacitor. For the higher frequency range, it should be a high-speed switching in each IC placed next to some 0.1 ¼ F or 0.01 ¼ F ceramic capacitor.
This paper aims to discuss the high-speed PCB design aspects. Although there are a large number of technical publications, seminars, press releases and online forums related to the topic, but this article aims at a comprehensive approach to PCB designers to provide the main design guidelines.
Several recommendations made by the following will help in the shortest possible time consistent with the EMC requirements of the design of circuit boards.
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