Tutorials to .com

Tutorials to .com » Mechine » Eda-pld » Mixed-signal FPGA verification process of the intelligent

Mixed-signal FPGA verification process of the intelligent

Print View , by: iSee ,Total views: 8 ,Word Count: 1718 ,Date: Thu, 25 Jun 2009 Time: 11:25 AM

In response to the market for higher performance, smaller size and lower system cost and power requirements, system designers is that the higher-level mixed-signal integration in their system-on-chip (SoC) designs. With the SoC design to increase the number of mixed-signal components, the basic functional verification for early silicon success with growing importance. FPGA system integration in a problem to add new features to improve the system integration side, such as the overall system cost, reliability, configuration and time to market and so on. In the core, this new paradigm - programmable system-on-chip (programmable system chip, PSC) integration of FPGA gates, embedded flash and analog functions in a single component can be programmed to provide the ability to truly process the ideal low-cost path, and the system designer can be used to quickly design and development of complex mixed-signal system.

The key criteria

Such as industry analysts said, FPGA is becoming a modern highly integrated SoC systems tools. The reason is obvious. As the silicon structure is pre-assembled, there are no NRE costs, and any products that may affect device performance or reliability of the change process should have been resolved. Most of the overall operation of the chip complexity (including the parasitic RLC of the impact of timing, etc.) have a complete adjustment features, and specifications of the data has been taken into account. Test cycle so that all can be dedicated to the design of the appropriate functionality. The next need is to minimize the design characteristics and enhance the function of the target time of verification. This reduction is through the intelligent combination of models (out of the system will not affect the overall behavior of the less important details) will be generated by the model have been fully aware of the placement process.

Increase in complexity

Field procedures for system integration is a new side. This new level of integration and a more in-depth the following advantages: the system designer to remove the system and the function of many components into a single PSB, the substantial simplification of system design; components will be substantially reduced significantly small number of size; and the integration of microcontroller core processors will be around from the main task, to reduce the workload of system requirements.

A new generation of PSC is the first case can be programmed into the representative of the logic of the market. It is the first FPGA reconfigurable hardware to provide basic benefits of state combined with flash memory, mixed-signal functions, as well as micro-controller technology. Open the contents of the increasingly complex integration of a smaller number of devices possible, but FPGA designers immediately, with additional challenges, one of which is to deal with mixed-signal design complexity. FPGA designers rarely have the opportunity to progress in these areas experience a profound, so what is to manage the complexity of these plans and to ensure the success of their first time on the way to do that?

The scope of an inter-professional and technical tools must be wrapped in the process.(、)。 Ideally this new system of pooling the contents of the complexity of design and traditional tools are basically the same as a tool for process flow.

Intelligent Process

Not only is the ASIC / FPGA designers of the system / analog design little practical experience, most of the system designers do not have the same experience in the design of digital logic. Therefore, the contents of the growing need for sophisticated design tools for intelligent process. This means that the tools are smart to start a different configuration and system components, combining them correctly, and prohibitive to all the scope of the complexity of cross-validation task to get a simple engineer. In this case, they must generate a FPGA. From the front-end (and to implement steps to the contrary), the complex nature of this in three important areas to be managed: component model, design (instantiation) and the verification process.

Component model

When the production of silicon components for the target model, the details of component behavior for the control system to verify the time required for the correct operation of the trade-off to be a prudent way. pld architecture in the simulation component is particularly important, and so the pre-assembled parts, even nature of the problem has been resolved or will be presented. Taken at the highest level, all the analog components are based on the number of components will be a strict code of conduct covered by the number of acts in a simulated mode. Tips is a complete act out the details of components, leaving only to make a decision on the target system with specific design features required. Processes in the PSC, according to the characteristics of the actual silicon data with the specifications of the electronic characteristics of analog functions, such as signal integration, A / D transfer functions and coupling effects. Including the importation of pre-scaling, differential gain, hysteresis, A / D control functions and output operations, such as the exchange of the basic acts of simulation will be extracted and placed in a digital simulator for the characteristics of system-level behavior Patterns of behavior in a rough figure.

Design example

Such a complex and skilled system design example of the need to have sufficient intelligence to enable designers to quickly produce flexible design environment. This is basically up to the target device's logic resources, the maximum allowed. These are self-supported graphics configuration resources can be very flexible capture, configuration, and examples in the design, but they are very simple pick-and-click action, does not require direct HDL code. Tool chain will be created at the same time frame, the resources will want to interconnect, and automatically create the necessary control mechanisms.

Intelligence to GUI-based tools are not required directly in the context of the user guide to achieve these steps. The focus of these tools are easy to use, and to provide rapid design development. Of course it does not rule out the traditional development of HDL code, which is familiar to users of HDL indispensable, they need to gates in the calculation of the largest of the design of the best, or the need for extensive customization of the design.

Authentication

Traditional mixed-signal ASIC development to follow a bottom-up approach. It involves two different groups: a research and development into the digital part of the RTL code, and the other in the transistor-level analog circuit implementation. In the verification, the designer of the general use of Verilog-AMS or VHDL-AMS's high-level full-chip simulation to verify system-level behavior, such as features, performance and delay and so on. This is closely related to the needs and the ultimate analog circuit behavior. interface to verify the level of the question, however, timing, signal integrity and power, such as transistor-level simulation is still the need for transistor-level simulation. This can also help avoid the model and the circuit between the accuracy or inappropriate link. In recent years the emergence of new levels of tools, to allow mixed-signal co-simulation environment in a designated mixed-signal SoC verification of components.

In the PSC process, mixed-signal simulation is not necessary. Treatment components such as analog functions within the separation of components of the general open-frame. The same components as manufacturers, the data specifications provided by the electronic characteristics of the analog functions of many information based on the characteristics of the actual silicon data. Act out a detailed simulation model generated by digital simulation in the whole (such as ModelSim, etc.), it can be achieved system-level verification. Analog input is real or a bit money in the simulation to the baseline test, the general test is generated by the benchmark tool.

With this level of taking, in view of mixed-signal FPGA provided by the basic authentication method and the figures along the standard FPGA is basically the same.

PSC typical designer during the design process will follow these steps: Libero generated in the integrated system functions and blocks; Synplify or Synplify PRO through the synthesis of design; ModelSim to verify the use of design; Libero Designer will use the design editor in the Fusion PSC by Lee back-end implementation; in ModelSim after the endorsement of the use of (back-annotated) again to verify timing.

This basic process so that Fusion users can use the proven methods in the design at any stage in the process of verification of mixed-signal system-level PSC acts like as simple as an all-digital chip. This process of integration based on the design of the remaining customers digital system analog input of a simulation system for portfolio-level implementation of the necessary work behavior.

The concept of SoC development professionals need a wide range of technologies, including analog design, digital logic design and system / structure definition. With the increased level of integration, the issue quickly becomes very complex and often involves the development of FPGA are usually not such a small group of professional logic / FPGA design engineering are.


EDA/PLD Articles


Can't Find What You're Looking For?


Rating: Not yet rated

Comments

No comments posted.