PCB on the FPGA of the Analysis of Simultaneous Switching Noise
Today, CMOS technology allows an FPGA device can have multiple I / O interface. At the same time, in recent years, has started to become a low-power high-speed I / O interface of the mainstream concept. Reduce power consumption is the most effective way to reduce the voltage, and voltage drop will lead to I / O interface to allow the noise by more than a small quantity. Therefore, FPGA users to quantify the chip, package and PCB system-level environment simultaneous switching noise (SSN) has become very necessary.
In this paper, a systematic SSN, the focus on the output buffer by the FPGA due to SSN. This noise is generally referred to as simultaneous switching output noise (SSO), and input buffer caused by different SSN. In this paper, the causes of system-level SSO, and a stratified system-level SSO modeling method. At the same time, this article will also explain how to model and frequency-domain SSO and associated time-domain measurements, and gives a number of the PCB to reduce design SSO.
The formation of system-level SSO mechanism
With FPGA-PCB is a complex system can be divided into circuit chip that contains the active part, with the support of embedded passive component alignment part of the package, and for the FPGA to provide connectivity with the outside part of the circuit board . In such systems, in order to understand the noise characteristics of the internal chip difficult. Therefore, the PCB and FPGA connected to the alignment of the proximal and distal to quantify SSO has become very valuable. SSO mainly caused by two factors: the power distribution network (PDN) impedance and switch I / O between the mutual inductance coupling.
From the system point of view, PDN included in the chip level, package level and board-level components, these components together for the CMOS power supply circuits. When a certain number of CMOS output driver circuit is open at the same time there will be a great influx of PDN current moment of emotional components in the circuit, resulting in a delta-I voltage drop. Parasitic inductance interconnect structure, such as ball grid array package solder balls and the power of the power supply PCB through-hole. This current will be rapidly changing in the power / ground plane between the incentive effect of the electromagnetic waves radiated electromagnetic waves from the PCB edge plane reflected in the power / ground plane resonance between, resulting in voltage fluctuations.
SSO resulted in another important reason is the mutual inductance coupling, especially in the chip package / PCB generated around the edge of the mutual inductance coupling. Chip BGA package on the PCB on the solder ball and through-hole are tightly coupled multi-conductor structure. Each I / O solder balls and their corresponding PCB through-hole and away from its recent grounding of the ball and the ground through-hole form a closed loop. When the number of I / O simultaneously change the status of the mouth, there will be transient I / O signal current flowing through these loops. This transient I / O current will also be time-varying magnetic field, which invaded the neighboring loop signal noise caused by inductive voltage.
SSO a good model should be able to embody the basic formation mechanism of SSO. Given in Figure 1 is a PCB used to predict the hierarchical model in the SSO. In the chip level, we need is limited complexity in the provision of online power cord and signal distribution precision current output buffer model. In the package level, for simplicity, can make use of modeling tools to be PDN model, respectively, and signal coupling model, but should give careful consideration to PDN and signal coupling between models. These two models play the role of a bridge connecting the chip package on the bump side of the output buffer model and the ball-end model of the PCB. The PDN model of PCB typically includes power / ground plane and its large capacity / decoupling capacitor, and the PCB model signal coupling includes a tightly-coupled through-hole arrays and the different layers of loosely coupled signal alignment signal. The two PCB-level model of interaction in the PCB through-hole array, crosstalk sensitivity is the noise from here into the PDN model, delta-I noise in turn, would reduce the I / O signal quality. This hierarchical modeling method to maintain a reasonable accuracy of the simulation, but also improved the calculation of such complex systems efficiency.
Figure 1: The PCB with FPGA schematic diagram of the SSO model.
Through the PCB design to reduce SSO
FPGA with the following response to the printed circuit board, to introduce two types of SSO based on the SSO mechanism to reduce the basic design method.
1. Reduce the sensitivity of the design method of coupling
Simulation results show that chip package / PCB interface emotional SSO wave coupling is the main culprit in the high-frequency peak. Size of a t × d of the signal from a signal loop through-hole and away from its recent grounding of the through-hole components, the size of the loop on the signs of the emotional strength of coupling, as shown in Figure 2. I / O interference with the greater area of the loop, the easier it will be generated by magnetic field interference with adjacent invasive loop. Interference with I / O signal loop area of the greater, it is more vulnerable to other I / O loop interference. Therefore, in order to reduce the crosstalk and the parameters of t, the design should pay attention to the use of thinner on the PCB, and PCB on the key I / O signals from the shallow layer of lead. At the same time, designers can also reduce the I / O through-hole and the ground distance between the through-hole to reduce the crosstalk. In the design shown in the figure, the designer will be devoted to a pair of I / O pad connected to the VCCIO plane to plane and to reduce interference and interference with pin-pin signal corresponding loop area.
Figure 2: Schematic diagram of the signal loop.
To assess the effectiveness of this method, we FPGA I / O Bank1 and Bank2 carried out two measurements, as shown in Figure 3. The two Bank of all I / O port are configured to the current strength of 12mA interface LVTTL 2.5-V, and through 50Ω stripline termination and 10pF capacitance.
Figure 3: I / O Bank 1 and I / O Bank 2 of the pin map.
In Bank1, the pin-pin AF30 is interference. In the FPGA design will be W24, W29, AC25, AC32, AE31 and AH31 This 6-pin through the programming is set to logic "0", which is connected to through-hole through the ground plane PCB. U28, AA24, AA26, AE28 and AE30 This 5-pin set through the programming logic "1", and connected to the VCCIO plane of the PCB. The other 68 I / O port to 10MHz frequency simultaneous switching, which is the interference of the pin. For comparison purposes, Bank2 not to W24, W29, AC25, AC32, AE31, AH31, U28, AA24, AA26, AE28 and AE30 these I / O through the programming set to VCCIO pin grounding pin or just be vacant, the other 68 I / O remains at the same time switch, as shown in Figure 3.
Experimental tests of AF30 on Bank1 bomb (ground bounce) than the G30 in Bank 2 to reduce by 17%, voltage subsidence (power sag) also decreased by 13%. The simulation results also verify the improvement. As a result of the emergence of programmable grounding pin ring to reduce interference and interference from the loop d, thus decreasing the SSO is expected, as shown in Figure 2. However, due to the signal-chip package can reduce the loop area, so the degree of improvement is limited.
2. Through the rational design of reducing the PDN impedance
PCB and the interface VCCIO pin grounding impedance between an FPGA chip for performance evaluation of the PDN is the most important criteria. Through the use of effective decoupling strategies and the use of thin power / ground plane on the input impedance can be reduced. But still the most effective way to reduce the ball will be connected to VCCIO power VCCIO plane the length of through-hole. Moreover, through-hole will reduce the power to reduce its ground with our neighbors constitutes a through-hole loop, so that this interferenceless I / O loop state change. Therefore, the design should be to VCCIO plane away from the PCB in the more recent top-level position.
Summary of this article
In this paper, the PCB with FPGA Simultaneous Switching Noise on a comprehensive analysis of simulation. Analysis results show that the package and PCB crosstalk interface PCB and packaging and distribution of the impedance of the PDN are two important causes of SSO.
Correlation model can be used to help PCB designers to reduce SSO, to achieve better PCB design. The paper also describes several ways to reduce the SSO. Among them, the rational distribution of the signal and make full use of programmable layer of ground / power pin may help reduce the PCB level perceptual crosstalk will VCCIO stromatolites in the PCB in the location of shallow PDN impedance can also be reduced.
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