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Remote endpoint 1553B bus data link layer protocol of the FPGA to achieve

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0 Introduction

For vehicles, ships, aircraft and other mobile platforms, a growing number of electronic devices, and more and more complex. Electronic equipment will be integrated effectively to meet to share resources and functions have become an inevitable trend. Electronic technology is integrated networking technology support, and mobile networking technology platform is different from the general LAN technology, which networks with particular emphasis on the reliability and real-time. 1553B bus 70 in the late 20th century, to adapt to the development of aircraft, aircraft from the United States the electronic systems within the network standards; later because of its high reliability and flexibility in other mobile platform has been widely applied. The domestic mid-80's last century has been in contact with such technology, the current research and its applications is expanding rapidly.

1553B bus standard formulated by the U.S. military. Agreement to support the standard chip DDC's BU have a 6517X, BU a 615XX series; HOLT's 61XX series HI a; UTMC companies such as BCRTM. These chips are integrated BC, RT, BM function, but these chips are produced by United States companies, the price is very expensive. To be able to use low-cost, very good reliability of this data bus, FPGA design and the use of remote endpoint data link layer protocol, through an external bus transceiver complete agreement 1553B chip function remote endpoint.

In the field of electronic design, programmable logic devices widely used for the design of digital systems bring great flexibility, an FPGA chip can replace hundreds of IC circuits. Altera developed the Cyclone series FPGA chips are cheap, powerful, and supporting the development of software Quartus Ⅱ is integrated timing simulation, the compiler, integration, optimization and other functions for the realization of a remote node 1553B bus communication protocols provided favorable conditions. The realization of the text in the remote endpoint of the 1553B bus data link layer protocol used VerilogHDL languages; using ModelSim simulation; using Quartus Ⅱ compiler, integration, optimization, and the A1tera achieve EPlC6 series FPGA.

1 1553B bus interface functions and their

1553B full name is: system of the aircraft internal time division command / response-type data bus multiplexing. Its physical layer, such as: transmission medium, shielding conditions, the coupling means and the input impedance matching input compatibility norms are so strict. 1553B serial data bus based on the form of pulse transmission, and its two-phase Manchester data to show that the form of code, the transmission rate of 1 Mb / s. 1553B data bus on the type of connection there are three kinds of nodes:

(1) bus controller (BC): the control data bus;

(2) remote terminal (RT): in response to BC command, the implementation of the relevant operation;

(3) Bus Monitor (BM): There are options to receive information on the data bus and save.

Each aircraft subsystem 1553B bus can connect to any system and its communications.

Transmission in the bus there are three kinds of character types: the command word, status word and data word. Word length of each word for 20, effective information-bit to 16-bit, each of the three characters for the first synchronization word, the last one for the parity bit. Effective information (16) and parity bit in the bus in the form of Manchester encoding, each representing the time 1μs. Account for synchronization prefix 3, or after the first is negative (the command word, status word) or negative after the first is (data word), positive and negative level each 1.5μs, simultaneously representing the first 50% of the market place.

Due to the different type of system, regarding the status of the order of words and word order of the words issued by the bus controller, and the state of the word sent by the remote terminal RT.

1553B bus as a remote endpoint, should be completed by the following features:

(1) serial bus microcontroller information can flow into the parallel processing of information or the contrary;

(2) to receive or send information, to identify or generate information 1553B standard characters;

(3) complete the microcontroller between the exchange of information, including address information of the distribution of 1553B, the word order or return to the status of word decoding, word, such as sending data.

1553B remote endpoint data link layer protocol needs to be done above the majority of end-1553B remote functions, including synchronization and detection of the first to add, Manchester code coding and decoding, the word order of word decoding and receiving data, status feedback and send and receive data word word, data buffer and the interface between the microcontroller and so on. Data link layer protocol of the internal registers used to operate a controlled manner, the upper micro-controller to achieve the adoption of procedures to read and write registers, to complete control of the agreement, and the internal operation is in accordance with the relevant state to register, so the design of , first of all, the definition of the relevant register, according to the width of data lines, all registers are defined as 16.

(1) control register: it completed an internal clock, the bus port selection, node-state setting, the state of the word reservations, and node ID, as well as the overall state of reduction, such as setting up and operating.

(2) an error register (ER): When the communication protocol in a parity error, data for errors, the number of receive data errors, receive FIFO error when sending FIFO error bit of their home place, the upper micro-control ER browser will know by reading the type of error.

(3) status register (SR): SR reflect the current data link layer protocol of the state, including a state of receiving data, receive FIFO length, sending FIFO length, receive error status, the status of interrupt signal nINT and nINTD.

(4) receiving a command word register (RCR): RCR for the preservation of the current command word received.

(5) Send the word vector registers (SVWR): The Register used to store the vector request bus controller words, the vector from the microcontroller to write the word.

(6) register to receive synchronization word (SYNDR): used to store data received with the word order of the data synchronization word.

(7) self-test results register (STRR): STRR used to store the results of the last self-test. In order to facilitate address assignment, the design of the transmit and receive FIFO are 16-bit register as a treat.

2 1553B remote endpoint data link layer protocol to achieve the overall design of the FPGA

1553B remote endpoint data link layer protocol is divided into the FPGA to achieve a total of four modules: Sequence Analysis module, the command analysis module, sending module and the upper cross-module. The realization of the entire agreement of the use of timing-driven manner, the clock frequency of 8 MHz, the following in accordance with the data entered on the order of the entire FPGA implementation of the agreement.

2.1 Sequence Analysis Module

The module receives from the transceiver to receive the signal sequence, one after another to synchronize the first detection, Cayman code decoding, parity, ID detection steps, the final resolution to the command module command information includes only the 16-bit data, as well as the characteristics of its characters. The realization of the process as shown in Figure 1.

Remote endpoint 1553B bus data link layer protocol of the FPGA to achieve

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Sequence Analysis of the first module of the bus into the first detected synchronization sequences, if effective, then to Manchester code decoding. Manchester code decoding is effective in detecting synchronization when the first started in synchronization, it effectively at the same pace after the first detection of the sequence 1 000μs every sampling time, and to decode the value as a sample value and at the same time to determine whether sequences in the sample took place when the hopping, If, then meet the Manchester coding sequence, otherwise the existence of that coding sequence error, and stop decoding and error register bit home, and the first sampling is effective at the same pace after the first detection of 250ns. After the completion of decoding parity, receiver module sequence for effective parity, if parity errors are discarded the sequence, while errors in digital home digital information; If parity is correct, then enter the ID detection part. Parity in VerilogHDL by XOR bit can be achieved.

When the correct parity, the receiving synchronization module on the basis of the first word has been detected in different types of operation. For the data word received by receiver module testing sequence after waiting for the value of register data word, if not zero, while the data Add to the receiving buffer, if you wait for the data word register value of 1, then first register Clear, and then the interrupt request signal home, and the final value of the Status Register Add send buffer, and to inform the sending module to send and wait for the data word register reset, otherwise the data, such as a word question the value of register by 1, wait The arrival of the next word. If you wait for the data word register value is zero, then that transmission errors, discarding the data characters. The word order, receive ID verification module to check whether the command received is distributed to the bus controller node. It to extract the received information sequence of 16-bit effective high-five, with the node ID comparison, the same as if we do not, then discard the sequence and wait for the arrival of the next sequence; If the same, then this sequence is bus distributed to the node controller command, save command, start the command analysis module.

2.2 Command Parsing Module

Analysis module to complete the order received to resolve the word order of the received data stored in the work. Order analysis module is the core of the whole agreement, which is responsible for the bus controller to command the nodes nodes are translated into the operation and implementation of relevant action. Its work processes as shown in Figure 2.

Remote endpoint 1553B bus data link layer protocol of the FPGA to achieve

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The assumption that the word stored in the command register CMD-REG [15:0] in order to resolve the first detection module CMD REG [9:5], if the CMD REG [9:5] is not for the whole or a full-0, on that bus controller to the data transmission node command; order analytical detection module will continue to CMD REG [10], and if it is 1, said bus controller requests the nodes send data at the same time with CMD REG [4:0] specify the need to send the data length; order analysis module in the order they received the relevant data and status register values into the send buffer, and to inform the sending module to send. If the CMD REG [10] bit is O, said bus controller requests the node receiving data, but also with CMD REG [4:0] specify the length of the receive data, and use CMD REG [9:5] specify the son of data reception node ID, the command analysis module in order after they receive the CMD REG [4: O] into the register to wait for the data word, waiting for the arrival of subsequent data words. If the CMD REG [9:5] for the whole or a full-O, bus controller, said transmission control command characters, and through the CMD REG [4:0] specify the way the corresponding command code. Way for the command code, command analysis module in accordance with the standard 1553B bus code on the different ways of home-related register bit operation.

Send Module 2.3

Order to resolve after the completion of all required state feedback or data distribution, and the completion of this function is to send module, sending module is responsible for the command module and receiver module to resolve the send buffer containing the data sent to the bus to get Figure 3 show, which includes the read data, resulting in reversed-phase character, Manchester coding, add the first synchronization, 2 MHz clock and data sent several of the buffers at the same time send the data as a result of the possibility of more than 2 bytes, it may also be the need to carry out the operation cycle. Send the following in accordance with the specific design of each part of the process. The first is to send buffers of the receiver when the send command to send the first module to send buffer to read the first two bytes, which is a state of two-byte characters, and then paste these two bytes on the status of the word label, continue to follow-up unit, to be completed after receiving just send the send data buffer length register by 1, and to send the data in the buffer 2-byte move. If the send data length register is not zero, continue to wait for the next delivery.

Remote endpoint 1553B bus data link layer protocol of the FPGA to achieve

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2.4 the upper cross-module

The last module is the top cross-module, the module with the microcontroller level information exchange, which is responsible for the microcontroller to write data Add the corresponding register, or by order of the upper microcontroller return relevant data . Interactive modules, including the upper edge of the main signal and the signal-level conversion, address decoding and read and write registers. Because the protocol module is used to trigger the edge of the signal, while the upper micro-controller is a signal to the FPGA-level signal, it is necessary to successfully complete the communication, on the need for conversion, here through the latch and the counters to complete. Address decoding is to decode the address received into the corresponding address register, and then write the data received or to register to read out the data to the data bus on Add.

3 Simulation and FPGA realization of

In order to ensure the feasibility of the design must be on the design of timing simulation. VerilogHDL achievement of the entire agreement procedures in Altera's FPGA development software Quartus Ⅱ prepared, compiled and integrated. Simulation of the entire process carried out in the Modelsim 6.0, the simulation process is as follows:

(1) receive data. Bus controller to send data to the realization of the two procedures: 0x1234 and Ox5678, the upper micro-controller to receive data in the realization of the procedures adopted by the upper cross-module data read out, the first of which contains a data length of receive data, can be seen through Figure 4 the entire process, the completion of the intended target.

Remote endpoint 1553B bus data link layer protocol of the FPGA to achieve

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(2) send data. Bus controller to send between the two procedures to achieve an order to send data to enable the realization of the feedback process related data that is in advance through the upper interactive module to write to achieve the process, the simulation process in Figure 5. Through Figure 5 can be seen in the realization of the procedure to receive an order to send out data about the delay time 4μs, in full compliance with the 1553B bus to the remote endpoint provided feedback signals delay.

(3) the general order. Bus controller sent to the general approach to achieve program command code, code, respectively: 000ll, 10010,01111 and 00001, the simulation process as shown in Figure 6. Can be seen that to achieve the correct procedures of the relevant information and feedback with the design requirements.

Remote endpoint 1553B bus data link layer protocol of the FPGA to achieve

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The design right in the simulation, the Quartus Ⅱ through optimized, integrated, and finally in Altera's Cyclone series FPGA on the achievement of concrete, and Freescale's 16-bit single-chip formed with MC9S12XDP512 remote endpoint 1553B through 1553B transceiver devices together into a 1553B bus system, the successful completion of the remote endpoint of the agreement. This shows that the realization of the use of FPGA programming 1553B remote endpoint communication protocol entirely correct to reach the desired objective.

4 summary and design versatility

1553B remote endpoint for the data link layer protocol procedures for the use of the FPGA to achieve top-down and bottom-up approach to the combination of design, language Veri1ogHDL; Modelsim and Quartus Ⅱ with simulation and synthesis. In the final, made a device-specific optimization once again, to shorten the design cycle and improve the system performance, and greatly increased the utilization of chip resources.

The design is highly versatile, with the external interface of the communication interface standard manner. It is for the upper micro-controller is a memory unit, the upper micro-controller to read and write to the relevant address to complete the entire communication protocol of the control, the application is very simple and can be packaged into modules, embedded processing, such as Nios Ⅱ browser has become an internal controller.

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