ARM high-speed flash memory-based MCU needs to deal with a wide range of embedded
As a result of the ARM7TDMI-S core, LPC2000 series mcu operating frequency of 60MHz, and other 8-bit products with more features compared to scalability. At the same time it increases with on-chip memory modules to achieve a "zero-wait access to" high-speed flash memory functionality, improve the efficiency of instruction execution.
In addition, LPC2000 rich peripheral interfaces, including UART, SPI, I2C, CAN, ADC, PWM, RTC, etc.. LPC2000 series MCU a broad range of applications, from network communications, motor control, automotive and consumer electronics that are suited to get involved.
Embedded system is a user-oriented, product-oriented, application-oriented, it is the advanced computer technology, semiconductor technology and electronic technology and the industry with practical applications of the product, so it is a highly intensive, innovative integrated system of knowledge. As embedded systems, it must be able to demand the application of hardware and software can be tailored to streamline the system to meet the needs of applications in functional, reliability, cost, size and other requirements.
Embedded systems embedded processor is the core part of the hardware, Philips ARM7-based balance of the introduction of 10 low-power high-performance LPC2000 series microcontrollers, to meet the growing demand for embedded market.
This series of new micro-controller LPC2114/2124/2
119/2129/2194, LPC2210/2212/2214, LPC2290 / 2292/2294 in the high-performance low-power provided the basis for enhanced communication and on-chip code protection mechanisms. As a result of a wide range of built-in serial communication interface, which is also applicable to communication gateways, protocol converters, embedded soft modems. 6 channel PWM for more complex motor control applications. In short Philips ARM microcontrollers embedded applications including industrial control, communications, security systems, medical equipment, aerospace, automotive and consumer electronics such as, covering from the low-end products to high-end embedded applications.
ARM7 microcontroller to the core architecture
To LPC2214 for example, its block diagram is as follows:
Figure 1, LPC2214 block diagram
LPC2214 support the CPU is a real-time simulation and tracking 16/32-bit ARM7TDMI-S processor, which processor is mainly used to compare power consumption and cost requirements of demanding applications. The use of three-line technology, to achieve efficient implementation of the directive. Apart from the ARM7TDMI-S processor supports the standard 32-bit ARM instruction set, and also supports 16-bit THUMB instruction set, THUMB code ARM code size of only 65 percent, but its performance is equivalent to connect to the 16-bit memory systems to deal with the same ARM Performance of 160%.
System-on-chip oscillator clock by external generated after a phase-locked loop frequency, the maximum operating frequency of up to 60MHZ. Memory controller chip through separate and CPU local bus interface, is designed to do so in order to avoid the uncertainty of the arbitration bus, the bus was delayed and the bus wait cycle, resulting in higher real-time.
Interrupt controller and external bus controller is a high-performance through the AMBA bus (AHB) interface with the CPU, external bus controller support for 8/16/32 bit external memory.
LPC2214 chip peripherals through the VPB bus, AHB to VPB bridge connected with the AHB bus. At the same time, it has a number of serial interface, including two 16C550 industry standard UART, high-speed I2C interface (400 kHz) and two SPI interfaces. It also has 8-channel 10-bit A / D converter (0 ~ 3V range), the conversion time can be as low as 2.44uS; 2 32-bit timers (with 4 capture and 4 compare channels); PWM unit (6 output); real-time clock and watchdog, 112 Universal I / O port (5V voltage tolerance); two low-power modes: idle and power-down.
Integrated high-speed flash memory chip
LPC2000 series of on-chip flash memory specifically designed for embedded applications. Using 0.18-micron process, and durable two-transistor cell write / wipe mechanism, can be written / rub ten thousand times, 128-bit wide array of optimization, zero-wait for the visit to enable the program to run at full speed. At the same time also provides the procedures for on-chip protection mechanisms to prevent code from being copied.
Figure 2, memory module speed up
LPC2000 family of microcontrollers to achieve zero wait to visit the high-speed flash memory, which is mainly due to speed up the on-chip memory modules. Figure 2 for the memory module to speed up the structural diagram. 128 through the width of the flash memory array with a separate processor local bus interfaces, the weekly period for the ARM core to provide four 32-bit instructions. This wait state without MCU can execute directly from flash memory instructions, thereby eliminating the general at the time of flash memory read latency. In order to address the changes in sequence of instructions, commands and data resulting from different treatment waiting times, the module has an internal prefetch buffers to avoid data read / write sequence to disrupt the address data to track buffer bypass and three functions Jump pieces of joint work, and two 128-bit memory width for parallel access and eliminate delay.
The role of memory modules to speed up depending on the size of the system clock. LPC2000 series on the access time for flash memory 50nS, for not more than the system clock of 20MHZ applications, in a cycle the contents of flash memory can be read out at this time no need to speed up the use of memory modules. The higher clock frequency, when the direct execution of code in flash memory, the system performance affected by the greater memory to speed up time-enabled modules, can be close to 4 times the rate of acceleration, the true realization of zero-wait for high-speed flash memory. LPC2000 directly as a result of execution from flash memory without the code during the period leading to the SRAM, this is not only dispense with the time-consuming and energy-consuming steps to start the system, but also saves expensive SRAM.
On-chip flash memory programming can be achieved through several ways: through the built-in serial JTAG interface, through the serial port in-system programming (ISP), or through In-Application Programming (IAP).
Rich external bus interface
LPC22XX family provides an external memory interface, which contains 24 address lines A0 ~ A23, 32 data lines D0 ~ D31 and the associated bus enable line; one can choose the width of the data lines 8, 16 or 32 to use Figure 3 for the 32 data lines 8/16/32 bit data width and line width of external memory connection diagram:
Map data 3,32 External Memory Interface Width
LPC22XX provided four independent and can be configured memory groups, each will have 16MB of address space, and may be SRAM, Pseudo-SRAM, FLASH, EPROM, BURST ROM or other I / O DEVICE to make the appropriate connection with the deposit check.
If the selection with on-chip flash memory products, the option is activated by the flash memory chip, or from external memory to start the process. LPC22XX series products, also provides a programmable wait cycles and idle cycles, the maximum allowed to insert wait cycles 32 and 16 idle cycles.
Vector interrupt controller
LPC2000 series of vector interrupt controller can support up to 32 interrupt request can be based on programming needs to be divided into 3 categories: FIQ, and non-vector IRQ vector IRQ. Fast interrupt request (FIQ) requests have the highest priority. IRQ vector with medium priority. Could be allocated to the level 32 of the 16 requests. Non-vector the lowest priority IRQ. This means that the different distribution mechanism programmable interrupt priority peripherals can be dynamically assigned and adjusted. Vector for any interruption, once the request, CPU can be had in a cycle and jump to the VIC reads the corresponding interrupt service routine address of the entrance, which will minimize interrupt latency.
Reference design program: Fiscal Cash Register
Fiscal Cash Register is a tax function with electronic cash registers, not only the operation and management of commercial enterprises the right-hand man, is also a permanent tax-store sales data collected on behalf of law enforcement. Automatically record with its internal but not the tax changes and erase memory, record the daily sales data and the tax liability is to the tax authorities to pay taxes and support.
China October 1, 2003 adopted the "national standards Fiscal Cash Register", the standard implementation of the birth of a huge market tax.
Fiscal Cash Register from the following components: Chinese display system; Chinese printing system; special tax treatment systems; peripheral device driver; power; with the chassis to ensure physical security.
Tax mechanism is based on a IC card issuance, management, reporting, maintenance, operating and other system components. Household goods sales tax in the tax records of cash registers and time-related information can be retained in the machine 5 to 10 years, can not be amended, can not be cleared. The data from the tax department with a dedicated IC card read out in order to inspectors.
LPC2214 given here for the main control unit to a minimum system reference design, the system mainly by the host MCU module, clock module, power module, control module, IC card reader module, Fiscal memory, status indication circuit, interface circuit and so on. Hardware structure as shown:
Figure 4, used the Fiscal Cash Register Hardware LPC2214 block diagram
Selection of Embedded Microcontroller Philips LPC2214, fully rational use of its real-time clock chip, external memory interface, UART interface and other peripherals. On-chip flash memory as a user program storage space, which features high-speed zero-wait to ensure that real-time operating system. Procedures for its on-chip protection mechanisms to prevent code from being arbitrarily changed and reproduction. The design of the structure of the whole system is simple and highly competitive advantage.
Fiscal Cash Register modular software design thought, the use of embedded controllers based on μC / os kernel RTOS operating system, the development of the user program be divided into the following parts: the main program, self-diagnosis module, IC card read write module, UART communication module, billing module, LCD display and buttons, such as man-machine interface module.
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