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ARM7 and FPGA combination

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ARM7 and FPGA combination in the industrial control and fault detection

Industrial controls often need to complete the multi-channel fault detection and multi-channel command control (which is very common set up multi-tasking), a separate CPU chip interface because of its limited number of external control and difficult to direct the prosecution to complete multi-task, so the use of ARM chips with the FPGA to expand the prosecution of a combination of channels is a very good option. Here ARM7 processor with Atmel Corporation (AT91FR40162) and ALTERA company's low-cost FPGA chips (cyclone2) a combination of tasks to complete multi-channel prosecution of a method.

Various parts of the functional profile

Figure 1 for this system connection diagram of the structure. As shown, ARM chip with the FPGA chip through the data between the bus, address bus and read and write control lines connected with the terminal PC through serial communication; FPGA device with the target bus through the command control and fault detection of the total line connected.

ARM7 and FPGA combination

Figure 1 System block diagram

1, fault detection and control of part of the command

Fault Detection: Fault detection channels (normal) signal to high (low) level means the instructions, which will be generated once the failure to maintain the same high level until troubleshooting. In view of this features in the ARM interrupt controller cycle of client inquiries, using methods from time to time to determine the status of channel failure. Procedures from time to time interrupted by ARM address bus in the FPGA in order to decode the detected channel lock-level value, and then returned by the data bus ARM judge, will judge the final results to the remote terminal. Query using the host rather than the way failure interrupted for two reasons: on the one hand, the control chip is usually limited external interrupt sources (the majority of four external interrupt sources), Multi-objective for the interruption of signal detection is difficult; On the other hand , or equipment as a result of detection by the short-channel interference level resulting from random inversion, resulting in failure to trigger interrupt, and then can not be interrupted by the trigger level in the channel back to normal fault signal when the revocation, they are forming a false alarm.

Command control: ARM chip made first to determine the host control command, and then through the address bus and data bus will be ordered by the state sent to the address decoder FPGA lock on the control channel.

2 ARM chips with the remote measurement and control terminal communications

As the only state orders and failure to send and receive signals, so the realization of the use of ARM serial communication with the remote PC, as the RS232 standard communication standards. However, in the first ARM chips will be TTL level conversion through the MAX232 chip-level standards for RS232, a distance of more than 15m for the full-duplex communications, but also in the send to receive the increase at both ends of a pair of RS232 to RS422 level conversion module, in order to increase communication distance.

3 FPGA internal function modules that

Detection and control of FPGA internal circuit structure as shown in Figure 2.

ARM7 and FPGA combination

Figure 2 FPGA internal logic structure

ARM chips ADDR2 ~ 0 bit address lines and chip select signals together to enable access to the address decoder for decoding decode1 after the 8-output (FPGA can be set within one of the largest output of the decoder module 256 routes, so in the practical application of can be extended to more channels), low 4-way channel used to send orders and high fault detection for 4-way access, read and write enable signal to control data bus.

ARM chips encoded signal received orders immediately to receive a break in service in the serial port and sent to the appropriate subroutine in the address (channel number) and data (ordered state) in the FPGA. Decoder effectively as the corresponding channel output of the latch clock D flip-flop, flip-flops and data are locked state as the selected channel after the completion of the corresponding control output.

ARM chip in from time to time have entered the interrupt service routine testing of all channels after the rotation inquiries, inquiries of the channel failure, fault signal by combining the selected channel signal sent to non-computing data port is read.

Attention to the issue of FPGA programming

1 Delay configuration

Through the address bus and data bus for command transmission and fault detection time, FPGA chip as the ARM to use common peripherals. ARM chip peripherals and access to well below the speed of memory chip, the ARM set to visit the right to wait for the cycle. ARM to provide the delay period of 0 to 7, through the debugger can find the right peripherals wait cycle, waiting for the system based on the actual test cycle is set to 5, the specific configuration procedures, see note ARM.

2 read and write enable signal to connect

From Figure 2 we can see that the write enable signal NWE and time to enable the data should be used as NRD signal line (DATA0 ~ 5) of the tri-state control signals to connect, even if the ARM chip in when no other peripherals can not be the default. Because the power of the ARM program time to load than the same system on the FPGA configuration time, and the detection and control FPGA and the ARM chip-channel data bus connected to, FPGA load data bus after the completion of the corresponding channel will be there logic-level value (not tri-state), which will lead to ARM chip in the chip-chip flash program or programmer power loader conflict with the FPGA (logic data is locked), resulting in correct positioning of the operation can not be targeted so that the failure to read and write.

ARM configurations and applications that

1 processor resource allocation

● Memory

AT91FR40162 a 256KB of embedded SRAM, 1024K 16-bit word consisting of Flash memory. SRAM through an internal 32-bit data bus connected with the ARM core, single-cycle access, Flash memory access through the external bus.

● system peripherals

EBI: External Bus Interface Control, EBI addressable 64MB of space, through the eight chip select lines (NCS0 ~ NCS3 independence) and 24-bit address line access to peripherals, address lines and four chip select lines (NCS4 ~ 7 ) multiplexing, data bus can be configured as 8 / 16-bit peripheral interface with two modes.

PIO: Parallel Port Controller, PIO control 32 I / O lines, the majority of multiplex pin can be programmed for general-purpose or exclusive choice.

AIC: Advanced Interrupt Controller, the realization of chip and external interrupt 4 external interrupt source interrupt management, the external interrupt pin with the general I / O multiplexing.

● external users

USART0 ~ 1: serial transceiver controller, support for 8-bit data transmission, can be asynchronous / synchronous transmission options, the chip pin and the general I / O multiplexing.

TC: Timer / counter, can be interrupted from time to time and count functions, the chip pin and the general I / O multiplexing.

2 memory address space after re-mapping the distribution of

After the CPU power will be the beginning of the first 0 from the address code of the implementation of instructions, and after power-on reset 0 address must be mapped to the next election NCS0 chip on the device, there must be connected to the NCS0 on-chip Flash to load initialization procedures and applications. Abnormal as a result of the suspension and the entrance of the addresses are fixed 0 ~ 20H, which are generated Jump to between 0 ~ 20H check the address of the corresponding procedures for implementation, in order to speed up interrupt response must be 0 ~ 20H address mapped to the chip RAM area, so in order to initialize the implementation of the re-mapping (EB1_RCR the RCB position 1), the internal RAM is mapped to address 0 on all response and the disruption of the entrance of the stack operations are mapped to the RAM area.

ARM7 and FPGA combination

Mainly as a result of re-mapping for chip Flash and RAM of address space in exchange for so-chip peripheral interface (EBI, USART, TC) corresponding to the memory address range in the mapping program does not change before and after, and re-visit the peripheral address after mapping the distribution. After the address re-mapping the distribution as shown in table 1.

3 application Interface configuration memory

EBI Memory: 8 EBI in the memory chip select (EBI_CSR0 ~ EBI_CSR7) visit to the parameters set up peripherals. Among them, 32-bit memory data bus width of 8 (16) settings, the number of wait state cycles 1 to 7 set, waiting to make energy (not enabled) set up, chip-enabled (not enabled) settings. FPGA as peripherals here so that they can NCS3 (can also be based on the actual choice of other free chip select lines), select the bus width of 16, so that can wait for a longer period of the cycle and set 5 (in accordance with debug options). NCS0 as a result of the default load Flash chip select lines, and Flash for 16-bit signal, wait for cycle 7, it EBI_CSR0 need to select 16-bit bus width, and 7 wait cycles can NCS0.

AIC memory: AIC memory to manage all internal and external interrupt, the correct initialization of this memory will open the corresponding interrupt assignment. AIC set operating parameters: application of serial communication mode for the asynchronous mode, serial data bit sent eight characters in length, baud rate communication 9600B / s, Serial Port Interrupt Priority 6 (interrupted by the low priority high 0 ~ 7), the receiving channel can be sent.

TC memory: memory from time to time interrupted from time to time need to set the length of 1s (each 1s inquiries generated fault interruption), from time to time to enable access and software trigger mode, set the timer Interrupt Priority 1.

Application Note 4

① main

#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) //EBIint main()
{AT91F_EBI_OpenChipSelect (
AT91C_BASE_EBI, //0x3, //NCS30x30000000+0x3f39); //Usart_init();//timer_init();//while(1){} //}

ARM processor registers in the complete application of the main program after initialization, the first call in the main program interface EBI-enabled function to set the parameters: in the process of setting the value of the memory base address (0xFFE00000), chip select settings 0x3 (NCS3 so can), NCS3 memory initialization; call function to initialize the serial USART controller: Open the serial port, serial transceiver channel initialization, set the serial communication rate; call timer interrupt function: Open regular interrupt, set disruption from time to time, set the trigger for software trigger; the last to enter the waiting cycle.

② order to receive the serial interrupt service routine

#define USART0_INTERRUPT_LEVEL 6//6
#define AT91C_US_USMODE_NORMAL AT91C_US_CHMODE_NORMAL//*(NORMAL)*//
AT91PS_USART COM0=AT91C_BASE_US0;//COM0char message[4];
// //
//*----------------------------------------------------------------------------*//
void Usart0_c_irq_handler(AT91PS_USART USART_pt)//{ volatile unsigned int *conp;unsigned int status;
int time;
volatile unsigned int i;
status = USART_pt->US_CSR &USART_pt->US_IMR;//if ( status &AT91C_US_RXRDY)//{
AT91F_US_DisableIt(USART_pt,AT91C_US_RXRDY);//AT91F_US_EnableIt(USART_pt,AT91C_US_ENDRX);//AT91F_US_ReceiveFrame(USART_pt,(char*)(message),4);//}
if ( status &AT91C_US_ENDRX){
AT91F_US_DisableIt(USART_pt,AT91C_US_ENDRX); // { if((message[0]^0xff)==message[1])//{switch (message[0])
{case 0x31 : {conp=(volatile unsigned int*)(0x1+0x30000000);//OPE1*conp=0x2;}; break;//0x31OPE1case 0x30 : {conp=(volatile unsigned int*)(0x2+0x30000000);//OPE2*conp=0x1;}; break; // 0x30OPE2case 0x11 : {conp=(volatile unsigned int*)(0x3+0x30000000);//OPE3*conp=0x2;};break;// 0x11OPE3case 0x10 : {conp=(volatile unsigned int*)(0x4+0x30000000);//OPE4*conp=0x1;};break; //0x10OPE4default:break;}
}
}

The procedure is for the serial interrupt service routine, the function of statements that refer to the Notes. Interrupt level is set to 6 (higher than the regular interruption), thus a priority in order to send inquiries failures (random order to control the emergence of failure always inquiry cycle); Receive buffer message [4] array type must be set to dynamic allocation, static data distribution will open up the data processor to the Flash chip buffer, which caused a disruption in processing time due to a result of access to serial port to send and receive timeout error. Because of space limitations, other procedures not described in 11.

ARM applications in preparation, it should be as little as possible in the main function of the use of cycle operation, the main function of the main application interface controller to complete the initialization, since the main function of non-stop cycle of operation will not only increase power consumption, and the frequent long interruption of service and switch to cycle between the main cause of instability run, it can be interrupted from time to time to complete the cycle of operation as far as possible with complete disruption.

Conclusion

ARM chip control functions combined with a flexible multi-FPGA hardware interface analog characteristics embodied in the engineering of its unique advantages, has developed into a popular model of the hardware architecture, along with the continued strong chip functions, which will make use of the advantages broader mandate to deal with to become more flexible and efficient.


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