Compact ARM-based image acquisition system
0V7620 is a CMOS image sensor, it has been widely used in the network camera, camera phones and other products. It is composed by the image acquisition system, the design of the more common method of OV5ll + or OV7620 with CPLD / FPGA. OV511 + or CPLD / FPGA acquisition of image data through the USB bus or dual-port RAM output to PC or mcu (ARM, DSP, etc.), by PC or MCU of image data for further processing. This article is designed with only one image acquisition system on the ARM chip OV7620 realize the function of control, timing synchronization, data acquisition and processing functions, the system is compact and practical.
1 The hardware structure
OV7620 is a CMOS color / black and white image sensor. It supports two kinds of continuous and interlaced scan mode, VGA and QVGA image format two; maximum 664,492 pixels, frame rate 30fp8; data formats including YUV, YCrCb, RGB three, to meet the general requirements of image acquisition system.
OV7620 features an internal programmable register settings SCCB power mode and programming mode. SCCB the system programming mode, continuous scanning, 16-bit RGB data output. System hardware block diagram shown in Figure 1.
Selection of ARM chips with the ARM7TDMI core LPC2210, the LPC2210 through the SCCB bus protocol simulation GPIO control register OV7620 function. Use LPC2210 interrupt pin 3 of the introduction of the OV7620 image output synchronization signal VSYNC, HSYNC, PCLK, to interrupt the output image data synchronization. OV7620 the YUV channels of 16-bit parallel output data through 16 high-LPC2210 data access. SST39VF160 and IS61LV25616AL for the expansion of the flash and SRAM, respectively, used for program memory and data memory.
2 concrete realization
2.1 OV7620 function control
OV7620 control the use of SCCB (SeriaI Camera ControlBus) agreement. SCCB is to simplify the I2C protocol, SIO-l is the serial clock line input, SIO-O is a bi-directional serial data line, respectively, equivalent to I2C protocol SCL and SDA. SCCB and I2C bus timing is basically the same, the response signal ACK it be called a first transmission unit 9, is divided into Don't care and NA. Don't care generated by the slave; NA generated by the host, as the SCCB does not support multi-byte read and write, NA must be a bit high. In addition, SCCB initial concept did not repeat, so SCCB read cycle, when the host chip End Address register, you must send the bus stop conditions. Reading or sending an order from the machine will not be able to respond to signals generated Don't care.
I2C and as a result of some of the nuances of SCCB, so the use of GPIO analog mode SCCB bus. SCL pin is always connected to the output set, and the SDA pin is connected in the data transmission process, by setting the value of IODIR, dynamic change pin input / output. SCCB write cycle of the direct use of I2C bus protocol timing of the write cycle; and the SC-CB time cycle, an increase of the conditions of a bus stop.
OV7620 function address register 0x00 ~ 0x7C (which is to retain a number of registers). By setting the appropriate register, you can make work in different OV7620 model. For example, the OV7620 settings for continuous scanning, RGB raw data output 16, the need for the following settings:
I2CSendByte () function to write register, its a macro definition for parameters of the OV7620 chip address 0x42, the first two parameters for the chip register address, the first three parameters for the corresponding register settings.
2.2 OV7620 clock synchronization
OV7620 has four synchronous signals: VSYNC (vertical sync signal), FODD (odd field sync signal), HSYNC (level sync signal), and PCLK (pixel sync signal). When using continuous scan mode, only the use of VSYNC and HSYNC, PCLK three synchronization signals, as shown in Figure l. OV7620 scanning for detection of the effective size of the window, but also the introduction of the HREF signal reference level.
LPC2210's three external interrupt pin 3 respectively as the input sync signal, the corresponding interrupt service routine for Vsync_IRQ (), Hsync_IRQ () and Pclk_IRQ (). In memory to define a two-dimensional array of image data storage, one-dimensional variable y that count for the level of synchronization signal; two-dimensional variable x that the synchronous signal for the pixel count. Image acquisition of the basic process is: When OV7620 good SCCB after initialization to enable the corresponding interrupt VSYNC in Vsync_IRQ () in the interrupt service routine to determine whether a data has been made. If so, then the loop in the main program in data processing; if they are not, then enable the corresponding interrupt HSYNC and y home for O. In Hsync_IRQ () in the interrupt service routine to determine the effective level HREF, if effective, then y plus 1, x set to O, and the corresponding interrupt to PCLK. In Pclk_IRQ () in the interrupt service routine to determine the effective level HREF, if effective, will increase in z, while a collection of image data pixels.
2.3 image data to match the output speed
In three of the OV7620 synchronization signal, PCLK cycle as soon as possible. When using the OV7620 system clock of 27 MHz, the default of PCLK cycles for 74 ns. The LPC2210 interrupt response time is much larger than this value. Maximum interrupt latency of the LPC2210 when asked for the 27-processor instruction cycle, the minimum time delay for the four instruction cycles, coupled with the interruption of service, on-site, such as recovery time, the completion of an interrupt response time is greater than 7 to 30 cycle instructions. LPC2210 system when using the highest frequency of 60 MHz, it is much larger than the response time of the interruption of O. 2 ~ 0,6 μs, so only the OV7620 down-PCLK. By setting the clock frequency control register can be set PCLK cycle around 4μs.
Image data access 2.4
OV7620 work when the main equipment in the way, it will be a continuous channel of the YUV to the output data bus. If the OV7620 in YUV channel direct LPC2210 the DO ~ D15 data bus, it will interfere with the data bus so that normal operation can not be LPC2210; 74HC244, etc. If the use of isolation, time-use data bus approach, which will greatly reduce the system operating speed, the LPC2210 can not take the bus in time data, resulting in incomplete image data. LPC2210 as a result of the data bus width of 32, while the Flash and SRAM with only low 16-bit data lines D0 ~ D15, the hardship this can be used in the method of Figure l, the high-idle data line 16 is set to D16 ~ D31 GPIO, for collection OV7620 output 16-bit image data.
2.5 The restoration of image data
OV7620 used when 16-bit output mode, Y-channel and UV channel output format of the data listed in Table l. L from the table can be seen, each line Y-channel and UV channel output on the turn of the duplication of data and his own new data. In line with, B only occur in odd-numbered column, R data appears only in even-numbered column.
Following a 55 pixel dot-matrix as an example, details of the restoration of image data.
First of all, the definition of a 515-byte type array, in Pclk_IRQ () interrupt service routine to read pixels 55 of image data; and then the image data interpolation, the odd-numbered points in the array of consecutive bytes into three B, G, 0, even-numbered points are deposited into the O, G, R; the end of the current line and each byte corresponds to the next line out for the average of each byte, you can calculate the RGB value of the current row. In each line, the odd-numbered points of R data and even data points of B can be, respectively, of its two points on both sides of the R and B data for the average to be.
In this way, an image to restore it. Direct deposit into a binary file (the system to the PC serial port to display output), or increase BMP bitmap file header information, biBitCouNt = 24 saved as bitmap file the DIB; LPC2210 can also be used on this image data for further processing , such as fingerprint recognition.
The system speed of image acquisition is subject to the LPC2210 interrupt response time, and if the use of a DMA controller, and has a higher processing speed of the ARM chip, can greatly enhance the speed of image acquisition system. For example, using ARM9 core with the S3C2410, the highest system frequency of 203 MHz, the completion of a DMA transfer time is about 30 ns. The default is less than the PCLK cycle 74 ns, can achieve 30 fps speed of image acquisition.
And with OV511 + or CPLD / FPGA compared to the image acquisition system, the image acquisition system has greatly simplified the system architecture and reducing system design costs and shorten the development cycle; image data acquisition and processing completed by the ARM chip, thus reduces the data transfer process of the probability of transmission errors and improve the reliability of the system.
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