Compressed digital video recording system designed large-capacity
With computer technology, multimedia and data communications technology is developing rapidly, the application of digital video has become an increasingly widespread, such as video surveillance, video conferencing and mobile TV. Enormous amount of digital video data is not conducive to the transmission and storage, to a very limited application. To resolve the video data storage and transmission problems, the only way is to compress video data. Common method of video compression MPEG series and H.26x series. Taking into account the compression technology maturity, cost, and the main purposes, the use of MPEG-1 compression standard as a design based on embedded ARM processor for digital video recording system. The system is applicable to video surveillance, video conferencing and other applications, can also be installed in the aircraft at the same time, the record for real-time flight training in the process of all kinds of information.
At present, there are a large number of PCI bus-based MPEG-1 video compression cards and PC-agency network video server rack. In contrast, we have designed a video recording system with low-cost, small size and low power consumption advantages.
1 System working principle
Video compression recording system focused on the design of embedded controllers and the overall portability. The system is mainly composed of 3 parts, namely, compression of the part and storage part of the control. Video recording system structure as shown in Figure 1. Which in part by the MPEG1 compressed video and audio compression circuit, the main function is to achieve the input of audio and video signal decoders, digital encoding and compression, resulting in MPEG1 Program Stream and Transport Stream; controlled in part by the smallest ARM system for the realization of the whole system control, data flow management and IDE interface control; stored in part by the large-capacity hard disk or CF memory card of the compressed data to achieve a long record of real-time.
Boot time, ARM processor for the entire compression system is initialized, first of all through the HOST port of the internal register configuration SZ1510 and SZ1510 the serial interface using I2C bus to the analog video decoder SAA7113H to initialize. When the set up of the compressed MPEG-1 format and data rate, the system started to work, audio and video signal processing chip AK4550 audio and video processing SAA7113 chip A / D converter, the output format 8-bit PCM digital audio signals and 4: 2-0 of YCbCr digital video signals into compressed audio and video collection SZ1510 processing chips, digital audio and video data into MPEG-1 format in line with a mixture of video files, last MPEG1 data streams in the control of ARM processor through the IDE interface into the hard disk or CF card. At work, ARM will continue to monitor the relevant signals, and the corresponding image by adding a sign to shut down until the receiver signal, the system automatically compress the end of the work.
2 Hardware Design
As the MPEG-1 compression algorithm takes a great deal of computing the amount of real-time using the software more difficult to complete, so in this system mainly depends on a dedicated chip to achieve efficient compression of video signals. At present, the commonly used MPEG-1 compression chip has VW2010, W99200F, WIS 7007SB such. The design is Zapex's SZ1510 MPEG-1 A / V encoder chip to complete their own audio and video synchronization code, 16-bit HOST interface to connect easily with a wide variety of microprocessors. In addition, the chip can also directly control the video decoder chip SAA7113H, audio decoder chip AK4550VT and SDRAM (KM416S1020CT-G10). CPU's ARM7TDMIS using Philips microcontroller core LPC2214, through its I / O port control interface IDE hard disk or CF card reader and storage of data.
Figure 1 digital video recording system block diagram
2.1 MPEG-1 compression circuit design
SZ1510 is a MPEG-1 and Motion JPEG image encoder. Its built-in video compression core is optimized for high-performance, real-time MPEG1 digital image compression, multi-functional, low power consumption, wide temperature range and so on; at the same time the integration of TI's high-performance dsp cores TMS320C54X can be based on MPEG -1 standard encoding of audio and video synchronization.
(1) set the clock synchronization circuit
SZ1510 is a small complex video compression systems, it is necessary to complete the audio and video synchronization, MPEG-1 video compression as well as the system of complex data streams, scheduling; clock relations more complex system design is a hard nut to crack. Clock configuration can be divided into the main clock, audio and video clock, video compression nuclear clock, DSP core clock as well as the expansion of several clock I2S interface. Its functions and relations:
◆ master clock. SZ1510 the master clock for the stability of 27 MHz (CLK). The internal clock in the chip was PLL1 frequency for 81 MHz, the video compression driver SZ1510 nuclear and SDRAM. PLL2 connected to the DSP core, through the software configuration to work in the 94.5 MHz, used for audio compression and data flow composite system.
◆ clock audio and video. Video clock from the video decoder, a typical value of 27 MHz. Audio clock from the clock frequency generated video.
◆ I2S interface clock. The system in the design of audio and video synchronization from the use of I2S interface model SZ1510 generated by the serial clock and frame synchronization signal.
(2) host (HOST) port settings
SZ1510 as from the equipment, by the host control, the HOST interface is SZ1510 control and data exchange interface. SZ1510 can choose to reuse or not reuse the Intel and Motorola bus type; no longer use the bus, but also can be divided into 8-bit and 16-bit. Specific host port from HCONFIG [1:0] pins and SysConfig  register configuration. In the design of the system, through the jumper to HCONFIG0 down, HCONFIG1 pushed to work in the Intel 8051 type of non-multiplexed 16-bit data bus mode.
2.2 LPC2214 microprocessor circuit design
LPC2214 is a 32-bit based on the ARM7TDMI-S, to support real-time simulation and tracking of the CPU; with a 16 KB chip SRAM, 256 KB high-speed embedded flash memory, 128-bit memory interface width and speed up the unique structure, so that 32 code to the maximum rate of 60 MHz clock running. Chip integrates a variety of serial interface. LPC2214 and SZ1510 the relationship between the interface and control as shown in Figure 2. In the design, it is necessary to pay attention to reading and writing SZ1510 is to maintain the timing synchronization with the internal clock. SZ1510 through CS3 strobe control word and data exchange.
Figure 2 LPC2214 interface relations with SZ1510
2.3 IDE Interface Design
Since the LPC2214 chip does not have the IDE interface, so the use of the system in general-purpose I / O port, analog devices have a read and write timing ATA, IDE hard drive to achieve reliable read and write operations. Figure 3 for the LPC2214 and IDE hard drive connection graph. Of which, P2.16 ~ P2.31 as a data line, P1.16 ~ P1.20 as its communication address and the election, P0.17 and P0.20 for the equipment and the status of the request reset signal, by P0.21 and P0. to achieve to read and write control 19.
Figure 3 LPC2214 with IDE hard drive connection graph
3 system software design
System software by the main program and several sub-procedures of the workflow shown in Figure 4. The main sub-modules are: SZ1510 and control settings, IDE interface drive and file system management.
Figure 4 System workflow
3.1 SZ1510 and control settings
SZ1510 a total of 128 registers, each register has an index number. SZ1510 work when non-multiplexed bus mode, the outside world access to the register IOAR and IODR through to completion. First of all, this visit will be written into the index register IOAR, and then write the data to write IODR.
SZ1510 set and control the process are as follows:
① to write interrupt enable register 0x40, so that disruption to Ready;
② Ready interrupt to wait for the SZ1510;
Ready to wait until after the interruption of ③ to register 0x1E the SZ1510 write 0x0A, set its internal clock for the DSP of 94.5 MHz;
Write to register 0x013 ④ 0x55, soft reset on SZ1510;
⑤ to the Interrupt Enable Register 0x0C write 0x40, so that disruption to Ready;
⑥ RDY interrupt pending;
⑦ Ready to be interrupted to initialize after the SAA7113;
⑧ soft reset on the SZ1510, 0x0B register write to the 0x55, at the same time to register 0x0C write 0x40;
⑨ Ready interrupt to wait until after the DSP to load internal SZ1510 binary code;
⑩ internal video compression to carry out nuclear SZ1510 binary code loading, the specific load, follow these steps:
◆ to register 0x08 write 0x04, sending the start command;
◆ interrupted to wait for Ready, Ready interrupt clear;
◆ Data in register 0x01 to 256 bytes to write;
◆ End of Data interrupted waiting for, and then clear the interrupt;
◆ code space search procedure is finished loading, if not, then continue to load.
3.2 IDE driver interface
The system uses a common LPC2214 programmable I / O port simulation ATA device to read and write timing, the realization of the hard disk read and write. Simulation is given here to write the steps to register ATA device (read the steps to register ATA device similar):
① System interruption, to prevent operation in the write register generate an interrupt;
② analog set GPIO pin ATA interface for data output state, ready to output data to the device data lines;
③ ATA devices set up the corresponding address register;
④ analog set GPIO pin ATA interface level data in order to write the value of equipment;
⑤ ATA device register write enable signal is low;
⑥ ATA device register write enable signal is high;
⑦ Cancel ATA device register address selection;
⑧ Set GPIO analog ATA interface data bus pin to enter the state, the release of the bus;
⑨ open system disruption.
3.3 File System Management
Used in the design of embedded systems is a small file system ZLG / FS , mainly used for data storage as a standard file formats and the management of the entire file system. At the same time, audio and video in order to facilitate the search and inquiry, and to prevent power outages caused by a large number of illegal unsaved data is lost, set up in the system each time interval (30 min) to compress the data stored in the system time to a new file named Lane.
After testing, the system can be a long record of real-time audio and video signals outside recorded compressed data streams in line with the MPEG-1 video compression international standards. In the design, the use of the compressed video stream rate of 1.5 Mbps, 1 hour of video data (1.5 Mbps / 8) × 3 600 = 675 MB, for a 40 GB hard drive, the system for close to 60 hours recording time. System, small size, low power consumption for the mobile environment for real-time audio and video data compression record time.
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