# FPGA-based iterative tomography reconstruction in the fractional approach to

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1 Introduction

Emission spectra chromatography (EST) technology is a non-interference of the original field distribution under test measurement diagnostic techniques, his physical quantities in thermal testing, plasma diagnostics, etc. has shown great advantages, particularly in the presence of the distribution of measurements, other methods is almost irreplaceable, is a measure of the distribution of three-dimensional flow field within the physical quantity of a common method.

Conventional tomography reconstruction techniques, usually using **software** programming directly on the computer to complete, it takes a very long time, unable to meet the real-time renewal of the speed requirements, researchers have now begun to study the hardware ( For example, FPGA and DSP) up to achieve tomography reconstruction techniques, such as: ART algorithm is implemented on the FPGA. However, since ART image reconstruction algorithms for noise suppression are less capable of complex and iterative, and there is division operations, together with the FPGA implementation is more complex. Simultaneous Iterative Reconstruction Algorithm - SIRT can effectively inhibit the impact of measurement error, iterative format, simple and widely used, but the method using FPGA (field programmable gate arrays) to achieve when it involves the issue of fractional operator . Because in the FPGA the data is stored in binary form of participation, operations, decimals computational problem is one of the major FPGA **application** difficulties of the industry to deal with the FPGA using fixed-point decimal mostly deal with, this method is effective, but **application** is very limited, for the reconstruction of the decimal in the chromatography, using fixed-point operation is unable to deal with.

This paper proposes a method of dealing with decimals, that is to be involved in computing the data into the binary IEEE-754 single-precision floating-point number, and then call the Altera open IP checking floating-point data operations, Altera's IP core is provided Altera Corporation rigorously tested and optimized circuit function modules in the design **project** is called IP core design not only reduces the workload, but also to a certain extent, to save the chip resources for real-time iterative tomographic reconstruction possible. SIRT algorithm is better than iterative ART algorithm is simple and easier to reduce the reconstruction error, improve the reconstruction speed, more suitable for real-time reconstruction. FPGA design using Verilog programming and call when the open IP core Altera combined approach to implementation, software design and integrated simulation in the Quartus Ⅱ 5.1 **development** platform to complete the final module gives some simulation waveforms.

2 SIRT algorithm

SIRT algorithm is iterative scheme as follows:

Where P is the measured data, WT is a projection matrix W, transpose, λ the relaxation factor, F is the reconstruction volume.

Physical meaning as follows: to take the measurement vector of the back-projection as the initial image, in order to k +1 times the estimated F (k +1), the use of k-estimate F (k) with corrected image. Corrected image is proportional to the estimated error of the first k-vector-projection WT * (PW * F (k)). Thus each pixel is actually a time when the school through the pixel values of all the rays and the accumulation of errors, rather than only with a radiation-related, is also the SIRT can effectively inhibit the measurement of the root causes of noise in the data. Since each pixel of the school will take place all over the joint contribution of pixel-rays, a number of random errors average out, so the calibration process is called SIRT-by-point correction. Relaxation factor in which the selection of error convergence curve would have an impact, if the environment remains unchanged, relaxation factor can be fixed. 3 IEEE754 floating-point requirements for

Standard floating-point word length by a sign bit S, index of E and non-symbol (decimal) of the normalized mantissa M constitute. Its format is as follows:

Consider a 1 sign bit, E = 8 Wei index width and M = 23-bit mantissa (not including the hidden one) consisting of floating-point expressions. 545.2510 now to study the single-precision floating-point format in the forms of expression. By the bias = 2E-1-1 calculated offset is as follows:

The definition of a binary floating-point algorithm IEEE754-1985 standard also defines a number of special number of other useful treatment, such as overflow and underflow. Index E = Emax = 1 ... 12 and 0 mantissa m = 0 combination is reserved for ∞, 0 is 0 index E = Emin = 0 ... 02 and m = 0 and 0 mantissa encoding, pay attention to the expression due to sign mantissa , are zero and negative zero codes are different, in the IEEE754 standard also defines two special number, but in FPGA floating-point algorithms usually do not support these other expressions. These other figures in the informal count and (denormal) NaNs (not a number, non-numeric).

Pretreatment of four decimal

IP core to calculate the data, input data and output data should be binary for IEEE standard 754 single precision floating point, so that requires doing floating-point before the first data processing so that measured values of P and the projection matrix W value is converted to IEEE standard binary floating-point numbers.

Preprocessing steps are as follows:

(1) For measurement data P, he was collected by the CCD, and by the 10-bit A / D conversion, so that measurement data is converted to 10-bit binary integer, and then through the data pre-processing module, the data processing into the binary IEEE-754 single - precision floating point, input to the external register P to wait for calls.

(2) For the projection matrix W, if a certain image size, then the projection matrix W is fixed and may first be generated and processed into **matlab** simulation of IEEE standard 754 for binary single-precision floating-point number, and then deposit into the W register, waiting for calls.

This is only part of the discussion dealt with by the FPGA, which is confined to discuss measurements of P pre-processing, and for the value of the W matrix can be processed by the Matlab program, will not go into.

Flow chart shown in Figure 2.

5 Simulation and Simulation

For the measured values P, he was collected by the CCD area array, and after a self-made 10-bit A / D conversion derived binary integer data in accordance with its characteristics, can use shift, and then press order to reorganize and be able to turn it into a IEEE standard 754 for binary single-precision floating-point number.

5.1 Module pre-P

Measurement data P for the binary integer, be converted to IEEE standard 754 format, only the data first test, if the data is positive then the sign bit S = 0, otherwise S = 1; and then find the "one", the maximum bit , set to "1" the highest level for the first L bits, then the reservation P [L-1: 0] as the IEEE standard 754 of the mantissa M of the high, and then I added "0" to 23, that is too mantissa M ; while the L with the value of index e, then E = e +127. Suppose P [9:0] = 0001011011, compared with "1" the highest level of P [6], to retain P [5:0] as a mantissa M [22:0] high, and then back fill "0", derived mantissa M, in this M = 01101100000000000000000, while the index e is 6, then E [7:0] of the size of E = e +127, namely the 133, that is, binary 10,000,101, where the S = 0, then the value of P transformed Pout [31:0] = 01000010101101100000000000000000, simulation results shown in Figure 3.

Obviously simulation results are correct.

In accordance with IEEE Standard 754 form, the measured data P and the projection matrix W, the value of pre-converted into the form of IEEE standard 754 after the operation can be carried out.

5.2 Realization of Floating-Point Adder

Two floating-point numbers are added together, set up two IEEE standard 754 single precision floating-point, respectively 01000000011000000000000000000000 and 01000000010000000000000000000000, that is, the decimal 3.5, and 3, called floating-point addition IP core, simulation waveforms shown in Figure 4.

Simulation waveforms can be seen from the sum of the result is 01000000110100000000000000000000, that is, the decimal 6.5, apparently the result is correct.

5.3 Realization of Floating-Point Multiplier

Two floating-point multiplication, the number of set two are 01000000011000000000000000000000, that is, the decimal 3.5, call floating-point multiplication IP core, to be simulated. The simulation results in Figure 5.

Simulation waveforms can be seen by multiplying the number two result is 01000001010001000000000000000000, as a decimal number 12.25, that is, the result is correct.

6 Conclusion

Through the above discussion and analysis, this paper presents FPGA-based treatment of fractional method is feasible, not only solved in the FPGA to achieve emission spectrum chromatography SIRT algorithm decimal problems, but also broaden the scope of application of the FPGA, making FPGA not only processing can also deal with decimal integers, breaking the previous FPGA can only be used when dealing with decimal fixed-point processing constraints, while this article through the clever use of rigorous testing and optimization of Altera's IP core and the combination of an open self-compiled Verilog program, so not only reduces the design of the workload, but also to some extent you can save hardware resources, increase **system** speed, real-time tomographic reconstruction of the emission spectrum step meaningful step forward.

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