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LPC2131-based CPLD CAN-Interface Design

Print View , by: iSee ,Total views: 28 ,Word Count: 1589 ,Date: Wed, 26 Aug 2009 Time: 4:02 PM

Introduction

Philips's LPC213l is based on ARM7TDMI-S high-performance 32-bit RISC microcontroller. It has all the advantages of ARM processor - low power, high performance and more extensive on-chip resources, but not integrated within the CAN controller LPC2131, but can not use CAN bus to communicate. In order to make LPC2131 can take advantage of CAN bus communication can be achieved through an external expansion of its functionality. At present, the more common approach is to LPC2131 external CAN controller design using CAN bus interface. LPC2131 with CAN controller interface circuit shown in Figure 1.

LPC2131-based CPLD CAN-Interface Design

This approach, LPC2131 through the GPIO port connected with the CAN controller SJA1000 data interaction. LPC2131 through the register IOSET / IOCLR to set the I / O port of the high / low state, although they could also set bit / down the selected pin, but not at the same time some mouth-line pulled the line of pull of certain port low. Assume that P0 [15:8] Initial state 0xa5, Ruo Qiang P0 [15:8] at the same time becomes 0x5a, must be carried out through IO0SET and IO0CLR twice. Program to achieve the following:

PINSEL0 = 0x00000000;

IO0DIR = 0x0000FF00;

IO0SET = 0x5a00;

IO0CLR = 0xa500;

P0 [15:8] will appear on the middle of the state of 0xFF. In the high-speed communication systems, these intermediate states may result in the loss. Although it can operate through IO0PIN to eliminate such an intermediate state, but the Philips company does not recommend this practice, unless absolutely necessary as far as possible not to use.

CAN driver interface to the serial interface chip and LPC2131 levels are matched with each other, so in theory can be directly connected to the two, using serial communication ways. Use of CAN bus communication, in the long-distance communicate, CAN bus termination resistors at both ends to be increased. Its role is to avoid data transmission also reflected back, resulting in the destruction of the reflected wave Er Shi data; the same time, can improve the Bus transfer anti-jamming capability. In theory, receive data signals at the midpoint of each sample, just reflect attenuation of the signal at the beginning of sampling can be low enough to not consider match. Principle is usually judged according to data rate and cable length matching, but in practice difficult to grasp, are generally based on experience in design.

Programmable logic device (PLD) is the 20th century, 70 years in the ASIC design developed on the basis of a new type of logic devices. The 20th century, late 80s, the U.S. introduction of Altera and Xilinx, respectively, a large-scale and ultra large-scale complex programmable logic device (CPLD) and Field Programmable Gate Array (FPGA). Since the beginning of the 20th century, since the 90's, programmable logic devices has been the rapid development of the highly integrated, high-speed and low prices, a gradual progression towards; its expanding application fields can be used for state machines, synchronization, decoding, decoding, counting , bus interface and strings and converted, and many other areas. CPLD can be used to improve system integration, reduce noise, enhance system reliability and lower costs.

CPLD technologies, provides us with an effective solution: the CAN driver interface with LPC2131 indirectly a CPLD, right CPLD functional programming, so that it is responsible for serial bus data transfer and the prevention of CAN send reflection.

Select Altera Corporation MAX3000A series model EPM3128ATC100-7 (referred to as "EPM3128") of the CPLD chip. This chip is compatible with 3.3 V and 5 V for I / O port. This way, LPC2131, EPM3128, and TJA1040 in the I / O levels are matched with each other.

1 EPM3128 interface definition

EPM3128 is set to bi-directional serial bus channel. Among them, two I / O port is defined as CANRXD (IN), CANTXD (OUT), are connected to CAN transceiver TJA1040 the RXD and TXD-side, constitute CAN bus receive data and send data channels; another 2 I / O port is defined as ARMRXD (IN), ARMTXD (OUT), are connected to LPC2131's RXD1 and TXD1 side, constitute the processor serial port to receive data and send data channel. The entire data transmission process, does not change the serial data protocols and formats, interface circuit are all TTL level, do not ask for any period of processing. Communications data validation, Baocuo were handed over to traffic at both ends of the processors. LPC2131, EPM3128, and TJA1040 interface block diagram shown in Figure 2.

LPC2131-based CPLD CAN-Interface Design

2 EPM3128 function realization

Figure 3 is the use of function block programming EPM3128 data transfer and shielding the internal logic of CAN send reflection. Figure txArm2, rxCan2 defined as the input variables, corresponding to the external ARMTXD, CANRXD pin; txCan2, rxArm2 defined as the output variables, corresponding to the external CANTXD, ARMRXD pin. The bus is idle, the bus state has been maintained at "1", that is txArm2, rxCan2, txCan2, rxArm2 the value of all "1." When you enter the bus received a state "0" signal that the bus began to transfer data. If the LPC2131 to send data, then the LPC2131 first ARMTXD port to send a "0" starting signal, take the bus and the next one clock starts to send data frames; if TJA1040 new data received from the field, then the port to send a TJA1040 first CANRXD "0" starting signal, take the bus and a clock starts to send the next data frame. In order to complete the normal communication process in the data bits from the serial port to the serial port transmission.

LPC2131-based CPLD CAN-Interface Design

Program CAN send a reflective shield that is shielded from the CAN bus receives the output bus reflex "0" signal, because the interface to be awakened from a high impedance state relied on a "0" start signal. If the LPC2131 is sending data, this time through the input port ARMTXD variable txArm2 send a "0" signal to the variable txCan2, sent from the output CANTXD. By bus, the effects of radiation CANRXD input received from the CAN bus to a "0" signal, and "0" signal sent to the variable rxCan2, at this time rXCan2 received the "0" signal is the wrong signal. The logic of judgments, the program will be maintained as a variable rxArm2, port ARMRXD remain high impedance state "1." Reflex "0" signals, while being received, but in CPLD internally shielded disposed of. If there is no shielding treatment, then this error "0" signal will receive the bus wake-up from the high impedance state, a direct impact on data communication. Program the use of D flip-flop has two aspects: First, buffer input and output, smooth signal burr; two control signals to achieve the functions, such as the output of the reset and synchronization.

Use QuartusII software compiler, and use simulation tools simulation. Shown in Figure 4, the baud rate of 115 200 bps, edit input points txArm2, rxCan2 waveform, view output point txCan2, rxArm2 waveform. To facilitate the knowledge map, simulation, data ports will be occupied transmission time parameter set 0.

First of all, demonstrate the effectiveness of the output waveform. Observed in Figure 4 txCan2 and rxArm2 waveform, you can see all the moment values are determined, and thus prove that the system is in steady state, the waveform is valid.

Then, the argument output waveform of the logic. According to the procedure of the logic design, txArm2 channel data transmission priority, and always maintain txCan2 = txArm2. From the simulation results can be seen, txCan2 waveform is fully consistent with the txArm2 waveform; when txArm2 channel is "0", the shielding rxCan2 input data, and keep rxArm2 output has been "1", observed in Figure 4 at any time all the input / the output waveform, we can see that simulation result is correct.

Finally, verify that the timing of the output waveform. This part of the program is a combination of logic design, that is, the output of all the changes with the corresponding input change. From Figure 4 we can see that the correct timing simulation results.

LPC2131-based CPLD CAN-Interface Design

Conclusion

Based on CPLD technology to achieve the LPC2131 and the serial communication between the CAN bus. The method is simple and good stability, suitable for use in multi-channel CAN bus serial communication system. The technology has been applied to practice, to accept the test of practice.


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