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Space embedded image processing technology

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Space age technology has not only promoted the launch vehicle, the application of satellite technology and deep space exploration technology, rapid development, but also enable the development of the Internet has become the foundation of space-based space network, an extension of 2 to 100 million 10 million kilometers of Mars, to promote the space-based embedded image processing techniques such as micro-electronics space the rapid development of application technology.

Embedded Image Processing Technology

Space-based embedded image processing technology, the characteristics are as follows: First, embedded, that is, size, weight and power requirements of high; Second, the complexity to deal with G-class frame pixels; Third, the reliability requirement to adapt to poor working environment, long life; Fourth, real-time and generally require the calculation of second-class time. In order to achieve these characteristics, the embedded computer space needs to function, structure and physical realization of the three study areas.

(1) unified architecture model

In order to meet the integration can improve the chip design cycle and reduce the requirements to IP-based design of nuclear technology and platform architecture from the functional to the co-design approach to development. As a result of non-control-flow complexity of computer architecture, low efficiency, the current structure of the computer system used to control flow architecture, in accordance with our classification of computer architecture model, control-flow architecture can be divided into three categories: First, instruction stream-based architecture, it is represented by the microprocessor architecture, in accordance with the instruction stream using Flynn and data flow logic of the concept of two categories A total of SISD, SIMD, MISD, MIMD four architecture; second is based on data flow architecture, it is based on ASIC (such as the Systolic array) circuit architecture represented by, because it is only the concept of data flow so that only two types of SD and MD, although as a result of the efficiency of ASIC circuits, but there is no processor and flexible in order to overcome this shortcoming, there is a static programmable FPGA circuit; three are based on the flow configuration (Configuration Stream) architecture, often called reconfigurable (Reconfigurable) architecture, which is dynamically programmable circuit, a total of SCSD, SCMD, MCSD, MCMD four categories.

Classification of these according to the logic of the concept of architecture can be used together, can have their choice of 1023 kinds of programs. On specific programs to achieve more in terms of, for example, different manufacturers of the instruction set of the processor is not the same.

The function and architecture co-design, through the functional architecture of the completed map, in order to ensure that the mapping of high-performance and unified, a unified architecture model, from the three aspects of a unified architecture : First, a Unified _ISA model, as shown in Figure 1, to the three from the instruction set architecture of the unified; Second, a high-level language to assembly language and compromise among the mapping language, to the compatibility of high-level language and readable, with the assembly language procedures for efficient and direct mapping of unity; three mapping through the middle of the programming language, can software component and hardware design elements to unify.

Space embedded image processing technology

Figure 1 Unified _ISA logic model concept plan

Specific architecture of the instruction stream, its SISD, SIMD, MISD, MIMD architecture four subset of the commands are unified into a SISD instruction set architecture, data flow and structure for the flow structure of the system by increasing the corresponding command, unified into a SISD architecture of the instruction set; In other words, Figure 1 in SIMD, MIMD, ASIC and MPP Unit four RC Device can be described through the software component. These soft components can be SIMD or MIMD architecture implemented directly, or can be automatically mapped into ASIC or circuit RC Device.

(2) virtual array of parallel computing

As the G-pixel frame-level needs of remote sensing image processing, MPP parallel computing has been the development of an array, as is always two-dimensional image frame, the corresponding processing element is also a two-dimensional array, as shown in Figure 2. Although the chip integration has been high, but can not be developed on a single chip frame G-class G-pixel processing element of the array, it is only by adopting the WSI technology to deal with the completion of one million yuan of the array. Therefore, it can only deal with the use of virtual element array technology to address the MPP program design and procedures to facilitate the readability of their own. In other words, MPP image processing procedure is based on the design of a virtual array of parallel computing, which is when the MPP program, always assume that Figure 2 in the grid array of the value of M and N is the dimension of the image frame size equal to , and the processing element array of the actual size of m × n is much smaller than M × N's, MPP program is automatically mapped to the actual implementation of the processing element of the array. For the characteristics of image processing algorithms, image processing, the MPP is usually calculated by the SIMD array architecture design. The corresponding design problems are: the location of processing element PE and the location of that choice, the use of PIM design solutions image processor and image memory bandwidth between the issues, as well as the issue of parallel resampling.

Space embedded image processing technology

Figure 2 M × N array of virtual processing element

(3) the physical realization of bionic technology

The mysteries of the universe and the brain's desire to stimulate the human space travel and tour the human body so that embedded computing technology from the traditional computing model, the development of the autonomic computing model to a natural mode of calculation. Traditional calculation of the chip technology has now developed to a single-chip multi-purpose function of a new stage of SoC chips, software technology from Structured Programming to Object-Oriented Programming, Component-based programming, as well as based on Agent programming.

August 1956, John. McCarthy made the first artificial intelligence (AI, Artificial Intelligence) concept, when he said: "The thinking of the times the machine will not be coming for 20 years," but now is still in the initial stage of artificial intelligence, only in the "cognitive science" and expert systems has been successful, this illustrates the difficulties of artificial intelligence. It is estimated that from 200X to 201X will be entered in the electronic age satisfied the 30nm, the autonomous mobile robot operation with the air of gravity to walk pronunciation, as well as shooting fish eye lens, such as the Bionic Autonomic Computing technology will be more perfect. Bionic Autonomic Computing technology is mainly from the use of fuzzy logic reasoning ability, neural network learning ability and genetic ability to calculate the optimal field of study, and the real challenge lies in changing and redefining the nature of computing hardware.

In many ways, the human body is one of the most effective computer, the nervous system of the body is satisfied as a result of (Na Sodium) and potassium ion (K, Potassium) ion movement across the brain and the nerve center of the body between the transmission of signals, interpretation and processing by the brain, which dominated human activities. It is estimated that from 201X to 20XX years into the 10nm era of nanoelectronics, quantum computing to promote the self-assembly technology, chemical technology, as well as DNA computing neuron fault-tolerant computing to natural computing technology to achieve bionic technology. In particular, molecular self-assembly technology, the chip has been made in the laboratory (ALM) and other practical results.

Concluding remarks

To sum up, we put forward from the functional architecture of a unified model of the structure will be able to effectively support the design of a virtual parallel computer program designed to deal with the array element, from the physical realization of a general research support Self-assembly technology, design platform. In short, SoC chips, nano-manufacturing and self-loading technology, will further promote the space age of the embedded image processing technology.

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