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The advantages of FPGA co-processor

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Traditional, based on general-purpose dsp processors and running the algorithm developed by the c language, high-performance DSP platforms, is moving in the use of FPGA pre-processor and / or co-processor direction. This latest development could provide significant for product performance, power and cost advantages.

Although the position is so obvious, but accustomed to the use of processor-based systems design team, will continue to avoid the use of FPGA, because they lack the necessary hardware skills to the FPGA with the Writers processor (Figure 1). Are not familiar with such as VHDL and traditional hardware design methods to limit or prevent the use of the FPGA, which often lead to design cost is too high, and the power consumption is too large. ESL, introduced a new set of design tools to address this design problem. It reserves of conventional hardware and software design approach, while helping the designers of the use of processor-based programmable logic to accelerate their design.

The advantages of FPGA co-processor

Figure 1 - DSP hardware platform

With FPGA co-processing to boost performance

Designers can take advantage of parallelism by the FPGA architecture arising from the use of flexible features, significantly increasing the performance of DSP systems. The usual design example include (not limited to) FIR filtering, FFT, digital down conversion and forward error correction (FEC) module.

XILINX VirtexTM-4 and Virtex-5 architecture provides up to 512 parallel multipliers, they can run at speeds in excess of 500MHz, providing 256GMAC peak performance of DSP. Through the FPGA to achieve high-speed parallel processing, while in the DSP to achieve high-speed serial processing can make the whole DSP is optimized system performance while reducing system power requirements.

With FPGA embedded processing to reduce costs

FPGA co-processor DSP with a hardware system for the C++ algorithm is within the scope of operations (such as DSP processors, FPGA configurable logic block (CLB) and the FPGA embedded processor division between the algorithm) provides a number of implementation methods . Virtex-4 devices provide two kinds of embedded processors - are often used as a control system of the MicroBlaze soft-core processors and higher performance PowerPC hard-core processors. By the FPGA architecture for parallel operation, can be directly used DSP data paths, or configured as an embedded processor, hardware accelerators.

The challenge for designers is how to provide hardware resources divided between the DSP-system operation, in order to achieve the most effective and most cost-effective. The use of FPGA embedded processor, the greatest benefits are not always obvious, but the hardware resources are indeed able to significantly reduce overall system cost. FPGA embedded processor provides such an opportunity: to all non-critical operations to focus on the embedded processor running the software, thereby minimizing the total amount of hardware resources required for the system.

C program to the system gate

In FPGA applications, the term "C program to the system gate" refers specifically to one of the following two methods to achieve - directly in the FPGA architecture to implement a DSP module or for the MicroBlaze or PowerPC 405 embedded processor to create a hardware accelerator (Figure 2).

When operating directly in the DSP data path in progress, the FPGA as a DSP module to implement operations, able to obtain the highest performance. This method first C code directly integrated into the RTL code, and then in the DSP data path of the module materialized. You can use the traditional HDL design methods, or by such as Xilinx System Generator for DSP tool for such a system to conduct materialized. This direct physical-based approach enables developers to minimize the cost of the highest performance.

The advantages of FPGA co-processor

Figure 2 - DSP hardware system C-program Implementation

The mainstream C synthesis tool to achieve performance comparable with hand-written RTL - but to do this, the need for C synthesis tool works and code style is a detailed understanding. In order to achieve the required performance, often need to modify the code, and add inline comprehensive instructions to insert parallelism and pipelining level. Although it is in making those improvements, but it can still greatly enhance design efficiency. C system model-driven design flow is still a major factor.

As an alternative, for the Xilinx embedded processors to create a hardware accelerator is usually a more simple way. In this method, still mainly use the processor to run the C program, but will have a significant impact on performance, hardware accelerators in the form of action to be placed into the FPGA logic implementation. This is a more biased in favor of software-centric design approach. However, this method will sacrifice some performance. Similar way with the DSP module, C programs are integrated into the RTL code, the difference is that the top-level entity is surrounded by interface logic to enable the bus with the Xilinx embedded processor connected to. This creates a hardware accelerator, which can be transferred to the Xilinx EDK environment, and is software-friendly C program calls.

Mapped to the C program on the hardware accelerator performance requirements are usually not so harsh. The goal here is to make performance than using pure software approach has been improved, while maintaining a friendly software design process. Although there are coding techniques, and integrated within the joint command, but usually you can not use them to achieve the required performance.

Design - an obstacle to adoption of FPGA co-processing

Correctly classified and the achievement of a complex DSP system, it takes a lot of time and effort to master the necessary skills. In 2005, Forward Concepts market research firm in the DSP design in order to determine the most important criteria for selection of FPGA to carry out a survey. The survey results show that the development tools are the most important selection criteria, as shown in Figure 3.

Survey results show that the use of FPGA co-processor to achieve the advantages of DSP hardware system has been fully endorsed by the user, but for traditional DSP designers, development tools, the status quo, as their obstacle to using this design method.

The advantages of FPGA co-processor

Figure 3 - 2005, Forward Concepts market research, "DSP Strategies: Embedded Trends in the ascendant"

The advantages of FPGA co-processor

Figure 4 - Xilinx ESL program design process.

Xilinx ESL program

ESL design tools to digital design at the RTL abstraction degree have improved on the basis of a step. Some of tools specifically designed to be C / C + + development system model mapped to the FPGA and DSP processor with DSP systems. The aim is to enable the hardware platform for software designers to become transparent (Figure 4).

This year, in order to fully address these obstacles, Xilinx and ESL tool vendors together the major launched a program known as the ESL cooperation projects. The main objective of this cooperation program is to give designers the ability to software programming, programmable hardware to enable them to easily implement their ideas without having to learn traditional hardware design skills. The program combines innovative ESL member institutions to speed up the product development process, promoting the designer uses the world's most advanced design methods.


Will be a tool for Xilinx ESL partners combine to provide a wide range of complementary solutions, these solutions have been aimed at a range of products, platforms and end-users were optimized. Xilinx, also concentrates on developing complementary technologies. For example, AccelDSP synthesis in the floating-point matlab algorithms developed to provide a method of hardware implementation, while the Xilinx System Generator for DSP enables the use of ESL design and development of the modules can be easily integrated Xilinx IP and embedded processors together. With several highly innovative partner in the work of programmers to achieve the desired FPGA design flow of the most efficient way.

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