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A STC12C2052AD improved single-chip voltage regulator control circuit

Print View , by: iSee ,Total views: 24 ,Word Count: 1853 ,Date: Sat, 22 Aug 2009 Time: 10:00 PM

ZXC10 communication in power system, the upper output of the PWM modulation signal frequency of 1 kHz, and power system requirements based on duty cycle PWM signal to the regulator. That is, the power output voltage 40 Vdc ~ 60 Vdc range of the PWM signal through the linear regulator. 5% duty cycle PWM signal corresponds to 40 ± 0.5 Vdc, 95% of duty cycle corresponds to 60 ± 0.5 Vdc. Before this function is used with the D / A to achieve a single chip. That is, single-chip PWM modulation signal input through the single-chip microcomputer to calculate the PWM signal duty cycle, PWM signal in accordance with the duty cycle and output voltage relationship, and through D / A converter to generate for regulating the output voltage offset, and finally the adoption of this offset and the amount of power output feedback to achieve a common role of regulator.

1 single-chip voltage regulator system

Through a D / A to achieve the single-chip voltage regulator system block diagram shown in Figure 1. However, as with the D / A more expensive microcontroller, which will increase the product cost. If the PWM frequency modulation signal, and then through a simple second-order active low-pass filter to generate the offset voltage regulator, it can be used without the D / A converter to achieve the single-chip voltage regulator, so that significant cost savings. The improved circuit block diagram shown in Figure 2.

A STC12C2052AD improved single-chip voltage regulator control circuit

A STC12C2052AD improved single-chip voltage regulator control circuit

2 STC12C2052AD the PCA / PWM operation principle

As a result of single-chip for STC12C2052AD in a clock / machine cycle, and there is an enhanced 8051 core, so the 8051 faster than the general 8 to 12 times faster. 2 The single-chip programmable counter array Road (PCA) / PWM, which used to capture PCA1 modules can be used to identify the input of the PWM modulation signal, PCA0 module for pulse-width mode (PWM), frequency can be achieved conversion. In addition, since the single-chip prices were relatively cheap, so the use of this single-chip microcomputer as a core control chip.

Single-chip 2.1 STC12C2052AD the PCA capture mode

STC12C2052AD series of single-chip programmable counter array PCA includes a special 16-bit timer, which can be two 16-bit capture / compare module connects. Each module in the programmable mode, four kinds, namely: rising / falling edge capture, software timer, high-speed output or pulse output can be modulated. Design, module 0 can be connected to P3.7 (CEX0/PCA0/PWM0), Module 1 is connected to P3.5 (CEX1/PCA1/PWM1). Register as a result of the content of CH and CL are free incremental PCA count 16-bit timer value, therefore, PCA timer module can be used as two hours of public benchmarks, and work through the program in 1 / 12 oscillation frequency, 1 / 2 oscillation frequency, Timer 0 overflow, or ECI input pin (P3.4). Timer count CPS1 made possible and the CMOD SFR bit to determine CPS0.

PCA module to work as shown in Figure 3 capture mode, the CCAPMn register CAPNn and CAPPn a must buy at least 1. CEXn on external input module (including CEX0/P3.7, CEX1/P3.5, CEX2/P2.0, CEX3/P2.4 I) sample of the jump, if the sample to an effective transition, the PCA hardware Counter Array PCA will register (CH and CL) to the value of load modules in the capture register (CCAPnL and CCAPnH).

Pulse width of 2.2 STC12C2052AD mode PCA

By all the PCA modules can be shown in Figure 4 Working model for the PWM output. The output frequency depends on the PCA timer clock source. Since all modules share the PCA timer only, so that they output the same frequency. Each module is independent of the output duty cycle changes, and use of the capture register (EPCnL, CCAPnL) relevant. When CL SFR is less than the value (EPCnL, CCAPhL), the output is low, and when the value of PCA CLSFR equal to or greater than (EPCnL, CCAPnL), the output is high. When the value of CL from 00 to FF when overflow, (EPCnH, CCAPnH) content will be loaded onto (EPCnL, CCAPnL) in. This would be updated to achieve non-interference PWM. Enable PWM mode, the module registers CCAPMn bit PWMn and must be home ECOMn bit. Since the PWM is 8, so the following formula can be used to calculate the PWM signal frequency:

A STC12C2052AD improved single-chip voltage regulator control circuit

A STC12C2052AD improved single-chip voltage regulator control circuit

3 PWM signal reception and conversion

3.1 PWM modulation signal receiver module

PCA1 module as a result of using the PC output frequency of 1 kHz modulation signal of the PWM frequency (because the higher the frequency, the more easy to filter), the PCA timer will be home base for the time 1 / 2 oscillation frequency. With PCA1 (P3.7) receiver module to identify the modulation of the PWM signal should be increased so that the work of PCA1 / falling edge capture mode, and open the PCA interrupt. Design, be the first work set in the rising edge of PCA1 capture mode, so that when the sample to the P3.7 pin at rising edge hopping, PCA0 counter PCA modules can be CH and CL registers array of values to the module's capture loading register (CCAP1H, CCAP1L). And then in the disruption of (CCAP1H, CCAP1L) the value of stored data to custom modules (UP_DATAH, UP_DATAL), and an interruption in the work mode is set to PCA1 falling edge capture mode, which in the sample to P3.7 pin when the falling edge hopping, PCA1 hardware modules can be PCA counter register array (CH, CL) value of the capture module loaded into register (CCAP1H, CCAP1L). After an interruption in the (CCAP1H, CCAP1L) the value stored in the data unit (DOWN_DATAH, DOWN_DATAL), and the use of double-byte unsigned number subtraction PWM modulation signals are obtained when the pulse timer for counting the number of:

N1 = (DOWN_DATAH, DOWN_DATAL) - (DOWN_DATAH, DOWN_DATAL)

PWM modulation signal as a result of the frequency of 1 kHz, the cycle T is 1 ms. Therefore, 1 ms can be set up in the PCA timer for counting the number of N2, the PWM duty cycle modulated signal is:

A STC12C2052AD improved single-chip voltage regulator control circuit

3.2 PWM modulation signal frequency conversion

PC output signal of the PWM modulation frequency of 1 kHz or so. Because of the relatively low frequency, directly after the ripple filtering relatively large, therefore, before the filter should be received first modulated signal into a PWM duty cycle is linear with the proportion of high-frequency PWM modulation signal, frequency conversion can be PCA0 (P3.5) PWM function modules to achieve. As the choice of crystal for 20MHz, it is optional Fosc / 2 for the PCA / PWM clock input source, so that the PWM frequency of 39.062 kHz.

In this way, when PCA0 module is set to PWM output mode, according to PCA PWM mode (PWM) of the working principle, when CCAP0L = FFH when, P3.5 output duty cycle of the PWM signal to 0, and when CCAP0L = 80H when, P3.5 is output for the 50% duty cycle PWM signal, when CCAP0L = 0 when, P3.5 will be 100% duty cycle output of the PWM signal. In this way, by the PCA pulse-width mode (PWM) available to the working principle of:

A STC12C2052AD improved single-chip voltage regulator control circuit

This type can be passed on to the frequency of 1 kHz for the PWM signal is converted to the frequency of 39.062 kHz for the PWM signal, the converted original PWM duty cycle of the PWM signal 1 kHz linear relationship between the ratio.

4 second-order filter circuit

Figure 5 shows the second-order active filter circuit schematic. By the amount of feedback power converter, we can see that when the regulator for the 1.5V offset, the power output of 40 V; when the regulator for the 3.0V offset, the power output of 60 V. Therefore, the PWM signal for the 5% duty cycle, adjusting the parameters of second-order active filter, and by regulating the R5/R4 to change the op-amp gain, and then adjust to changes in RW1 benchmark op-amp, so that partial VS shift to 1.5 V; and the PWM signal duty cycle to 95% of the time, so that offset VS for 3.0 V. This would enable the PWM signal duty cycle of 5% ~ 95% change, so that the converter output voltage is 40 Vdc ~ 60 Vdc linear changes in the scope.

A STC12C2052AD improved single-chip voltage regulator control circuit

5 Simulation

According to Figure 5 for PSIM simulation, the simulation parameters can be set to: R1 = R2 = R4 = R5 = 10 kΩ, R3 = 20 kΩ, R6 = 2 kΩ, R7 = 1 kΩ, C1 = C2 = C3 = C4 = 104 pF, as shown in Figure 6 so as to arrive at a specific duty cycle waveform of Vs.

A STC12C2052AD improved single-chip voltage regulator control circuit

Other specific duty cycle (D = 5%, 20%, 40%, 60%, 80%, 95%) record the simulation data listed in Table 1. As shown in Figure 7 is the voltage regulator circuit and the PWM signal duty cycle regulator Vs offset curve. Can be seen from the graph, the linear relationship between changes.

A STC12C2052AD improved single-chip voltage regulator control circuit

6 Conclusion

In this paper, by increasing the frequency of PWM modulation signal, and then combined with second-order active filter circuit to achieve a frequency to voltage conversion. The conversion can be in range of 40Vdc ~ 60Vdc to power ZXC10 communications PWM output voltage signal through the linear regulator, such an approach would avoid the use of expensive D / A converter module, which can save costs. At the same time also increased the value of the power project.


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