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ISP-based image processing system of the PLD hardware design

Print View , by: iSee ,Total views: 21 ,Word Count: 1316 ,Date: Fri, 21 Aug 2009 Time: 10:02 AM

Introduction

With the application of image processing technology popularization, and its increasingly wide range of applications. In the medical, military, public security and other fields, especially in recent years in industrial automation, industrial testing is widely used. At present, most of the image processing system combined with the use of computer video capture card and camera head of its hardware system, this hardware structure is not complacent about the complexity of dealing with simple image processing system is clearly inappropriate.

At present, EPLD chip more and more internal resources, pace of software development is also better to gradually expand the application. It is generally agreed that the future of many electronic systems, will be CPU + RAM + EPLD characterized the structure. Imaging systems to the development of small-scale. How to design a simple, low-cost image processing system is to image processing technology applied to broader areas of urgent need.

This article describes the system is demand for this kind of developed.

ISP-based image processing system of the <a href=pld hardware design" />

1 design program

The entire system by the camera, the image input unit, image storage unit, the image processing unit, image display unit and the drive control unit composed of several parts. Image processing system block diagram shown in Figure 1.

The image processing system for Atmel's 89C55 central processing unit, system clock is 20MHz. Image Acquisition ISPLSI1032E provided in part by the image storage RAM address signal and image acquisition matrix of the clock signal. According to the needs of each frame image can be divided into 256 × 256 or 512 × 512 dot-matrix, in exceptional circumstances may also have recourse to 256 × 128 or 512 × 256 screen half way. In the image output unit may be superposition image and display the output menu, constitute a visual menu.

Furthermore, in order to adapt to industrial inspection and industrial automation applications, the system was designed drive control circuit can be output and analog switches. Basically able to adapt to a variety of occasions to control.

2 Hardware Design

2.1 ISP device development

ISP devices in addition to a general PLD device with the ease of use, performance and flexibility of FPGA, high-density, the most important one is its in-system programmable technology, ISP can be a state of blank welding to circuit board. ISP has installed any of the circuit board devices, as long as the PC and downloaded through the cable, you can upgrade the new programming code, and all work can be continuously carried out under the premise of power.

ISP (In System Programming) technology is the Lattice Semiconductor Corporation provides the first from a can in the product design, manufacturing process, every aspect, even in products sold after the end-user at any time of their devices, circuit board or the entire electronic system logic and functions of configuration, or the reorganization of the latest technology.

In the system development process, the image acquisition is the core of the video signal by the A / D conversion result of the memory storage, that is, how to produce video signals in accordance with the address signal memory. After the required estimate of the number of logic gates, we have adopted to address generator ISPLSI1032 and other logic circuits.

ISP-based image processing system of the PLD hardware design

2.2 The selection of image acquisition timing

Here, to 256 × 128 dot-matrix as an example to show the emergence of image acquisition timing.

A0 ~ A7 that in each line of the address in dot-matrix, A8 ~ A14 address line, said. Effectively signal their deeds and address A0 ~ A7 timing as shown in Figure 2, the market signals and A8 ~ A14 Address timing shown in figure 3. share this 256 × 128 = 32 768 storage an image storage unit.

If you need to capture images, by the ISP issued by the CPU to the START signal, the ISP to disconnect the CPU's address line of RAM images, images generated by the RAM's ISP address A0 ~ A14. End SIP produce an image of the address, an END signal output to inform the CPU has finished mining plans, and the RAM address lines and data lines to the CPU, for its image processing.

System a total of four 32K × 8bit of RAM (62256), of which:

For the image frame buffer RAM1;

RAM2 flag for the graphics for the image of the mark;

RAM3 memory interface for the menu;

RAM4 for the system memory for storage of intermediate data handling and processing of results.

Figure 4 Schematic image acquisition part.

In actual use, CPU of RAM1, RAM4 and RAM2, RAM3 time of the operation is carried out. Scanning period, CPU to operate RAM1 and RAM4 to carry out the calculation and the results of image processing; in the flyback period, were carried out in the set menu and mark. ISP of RAM2 and RAM3 operation period in the scan, carried out the menu and mark and image of the synthesized output.

ISP-based image processing system of the PLD hardware design

Lattice of ISPEXPERT in 90's at the end of the 20th century introduced a complete integrated development environment of the ISP. It has 500 components for macro calls in support of VHDL, Verilog-HDL, ABELHDL schematic compiler and integrated development of software; ISP devices can be used for logic design and optimization, logic mapping, automatic placement and routing to generate a fuse map download documents and programming. In addition, it can carry out the design of digital systems functional simulation, timing simulation and static timing analysis.

From the user's point of view, ISPEXPERT than Synario software Workview office and more powerful, more convenient operation.

This system omitted ISP1032E complex chip, a large number of logic circuits using VHDL language programming, through the development of integrated development environment ISPEXPERT not only save a lot of hardware debugging time and a reduction of mutual interference between lines. More importantly, saving time re-copy the board, significantly reducing product development cycle.

VHDL part of the preparation procedures see supplementary version of our website. http://www.dpj.com.cn

Concluding remarks

ISP-based and single-chip image processing system consisting of a simple structure, high integration, small size, low price and so on, especially for image processing functions with the embedded system development. The system has been used in practice to obtain good results.


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