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Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

l Introduction

GMSK modulation as a result of the power spectrum with very good features, better BER performance, to meet the mobile communication environment adjacent channel interference on the stringent requirements, so as a GSM, ETS HiperLANl and GPRS standards, such as modulation system.

GMSK modulation technique currently there are mainly two methods to achieve a dedicated use GMSK ASIC chip to complete the typical products such as CMX909 with the FX589 or FX019 to achieve MC2833 or GMSK modulation. This method is characterized by simple, controlled rate of base-band signal, but the modulation carrier frequency is fixed, there is no scalability. Another method is to use software-defined radio thinking of using the method of quadrature modulation in the FPGA and dsp platforms. Which also includes the realization of the two means is the direct decomposition of a single pulse in response to points of the Gaussian filter is divided into transient and steady-state part of the information through the accumulation phase to achieve; another track the use of frequency synthesis, through the sampling Gaussian filter to the basic track of the rectangular impulse response as a look-up table into the ROM, and then through the FM modulator to achieve. This thinking of the realization of the use of software radio GMSK modulation method has the advantage of variable modulation parameters, but due to a software design involves the Gaussian low-pass filter, phase integral and trigonometric calculations, so difficult to change the modulation parameters to achieve complexity. In summary, this paper presents a FPGA-based CMX589A and GMSK modulator design. Compared with the traditional method with a simple, easily controllable modulation parameters and software features such as easy to cut, suitable for CDPD, and other non-central station communication system and has important practical significance.

2 System hardware design

System hardware includes three parts: the expansion of single-chip controller and its peripheral keyboard and liquid crystal display module, Gaussian filter module, as well as the FPGA modulator module, system hardware structure as shown in Figure 1.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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System as follows: After the power system, FPGA completed initialization, LCD interface prompts the user to input control information, the system output at the same time fixed-frequency sinusoidal carrier, indicating that the normal work of system; users by controlling the menu prompt, enter the control information from the keyboard (for example, base-band signal symbol rate, the system parameters of Gaussian filter, BT values and carrier frequency modulator, etc.); control information through the main controller module sent to the Gaussian filtering and modulation module; FPGA modulator module According to receive the A / D converter input signal frequency range of the value of the control word in order to complete the base-band modulation signals.

2.1 Gaussian filter module design

Gaussian filter modules CMX589A produced CML ASIC has wide receiver speed base-band signal. In this design, to provide two CMX589A external crystal frequency, 25.576 MHz, respectively, and 8.192 MHz, through the jumper control. CMX589A control of the P2 and mcu pin connected to control the mouth of the filter parameters, which ClkDivA, ClkDivB with an external clock with the common decision of the baseband Gaussian filter symbol rate, set up as shown in table 1. BT-pin control of the system bandwidth Gaussian filter, when set to "l", the system BT value of O. 5; when set to "O" when, BT value of O. 3. Gaussian filter to the working process: First of all, according to the needs of different systems to set the base-band filter-symbol rate and bandwidth BT value, and then need to Tx Data pin access code modulation element of the base-band signal, at the same time to the Tx Enable high home through TxOut be able to receive the Gaussian base-band signal filtering.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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2.2 modulation index for the O. 5 Design of FM Transmitter

FM transmitter by the FPGA with A / D, D / A to achieve. Cyclone series FPGA selection EPlC6Q240C8, it is a mixture of SRAM manufacturing low-voltage chip FPGA. A / D using TI produced 8-bit ADC TLC5510, D / A DAC 10 is used THS5651A, to complete the high-speed data conversion. FM transmitter for the system clock 20 MHz, at the same time made available to the D / A THS565lA as the conversion clock. A / D conversion clock from the FPGA to provide, after the system clock frequency to the A / D converter 1 MHz clock work. At the same time, the adoption of SCM P3 I 2 b of the frequency control digital and 1 b of the "Enable" control bit with the FPGA connected to the modulator to control the center frequency of four kinds, namely, 20 kHz, 200 kHz, 2 MHz and 20 MHz Center frequency setting as shown in table 2. When the carrier center frequency is set to 20 MHz, the system clock through the FPGA to achieve the internal PLL frequency.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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2.3 single-chip controller design

AT89C51 single-chip controller, expanding outside the LCD, 4 * 4 matrix keyboard, and interface with the MCU connected to P0 and P1, P2 I SCM Gaussian filter and connected to the control line, P3 mouth and FPGA connected to the control of the center frequency transmitter.

Keyboard and LCD display module to deal with: the realization of human-computer interface using the keyboard, the keyboard scan module to shake, batter, and the signal processing function keys. Users need to adjust system parameters, and through a combination of LCD monitors to display the current parameters of modulated signals in order to make the system more operational.

Function of parameter setting module: This module is responsible for processing keyboard input data, in accordance with user instructions to select the appropriate system parameters (such as base-band signal of the symbol rate, FM modulator center frequency, etc.). Table 3 in the Gaussian filter module for the 8.192 MHz clock, the single-chip control system parameter setting filters.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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3 system software design

System software consists mainly of two parts: single-chip control module and the FPGA to achieve modulation index for the O. 5 FM modulator module. System software flow chart shown in Figure 2.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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3.1 single-chip software design

The main control module including the expansion of the matrix keyboard, LCD liquid crystal display, parameter control modulator.

Single-chip system controller as follows:

Single-chip initialization, LCD display the Start menu, including the "Gaussian filter parameter setting" and "FM modulator parameters," the two options;

Entered the "Gaussian filter parameter settings" sub-menu, including "system bandwidth settings" and "base-band symbol rate set", respectively, can set up two kinds of different filter bandwidth and eight kinds of base-band symbol rate, single-chip under the system settings in the P2 port output control information;

Enter "modulator parameters" sub-menu to set the "center of carrier frequency modulation", you can set four different carrier center frequency, and P3 single-chip FPGA I control the center of the modulation carrier frequency.

3.2 System modulator

FM modulator using DDS thinking to achieve in the FPGA platform. DDS (Direct Digital Frequency Synthesizer, Direct Digital Synthesis) is a new type of frequency synthesizer technology, have a high frequency resolution can be achieved fast frequency switching. DDS system is mainly by the system clock source, phase accumulator, sine look-up tables, D / A converters and low-pass filter composed of compensation, the system structure shown in figure 3. DDS phase accumulator which is the core of the system, which by the N-bit adder and the composition of N-bit phase registers. Each to a reference clock pulse, N-bit adder will be accumulated frequency control word and the phase output devices add to the sum of the results to the phase of the input register. Register on the one hand, the output phase of the phase data back to the input of the adder so that the adder in the role of the clock pulse to continue with the sum of frequency control word, on the other hand, the output of the phase data will also form as a waveform storage enter the address. Waveform storage table to enter the address phase information into a waveform data mapping, and finally, after DAC and low-pass filter the analog signal received.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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The design uses a 20 MHz external crystal oscillator as a clock source, the system using the phase accumulator 40, so the frequency of word 40 is taken, so the frequency resolution of the system shown in the following style:

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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FM modulator to the frequency of the completion of the conversion rate is the key to system design. For example, setting the rate of base-band signal to 8 kHz, the center carrier frequency of 200 kHz (fword = "10995116277"), in order to achieve a 0.5 modulation index for the FM modulator, FM modulator frequency deviation of 4 kHz. FPGA in accordance with 8-bit A / D converter input signal amplitude value of the word select the appropriate frequency to control the frequency of the output signal of the completion of the FM function. The center carrier frequency of the corresponding A / D converter center amplitude a in = "10000 0000"; when the A / D converter input to OV (that is, a in = "0000 0000"), the corresponding output frequency modulated signals for 198 kHz (fword = "10885165114"); when the A / D converter for full-scale input 2 V (ain = "1111 1111"), the modulator output frequency of 202 kHz (fword = "11105067440"). The frequency from 198 kHz to 202 kHz is divided into 255, etc., to convert the frequency of the corresponding frequency of 40 words, then A / D converter 256 of the 256 frequency and amplitude of the word-one correspondence. In each system clock cycle, frequency control word 40 and the phase accumulator value into the sum of the results of the phase accumulator. As the selection of the ROM look-up table for the 10-bit address lines, so check the high phase accumulator 10 as sine look-up table address. Cyclone sine look-up table to use to complete the internal look-up table ROM module design for the 10-bit word length, and the selected DAC to match the median of the data.

System, the magnitude of the input signal conversion and frequency of the core code is as follows:

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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Which, f_mid for the center frequency modulation signal, fm_frerom for A / D input signal amplitude value and frequency offset of the mapping relations between the system to receive signals in accordance with the magnitude of the value of the corresponding change in the frequency offset modulation signal modulation in order to complete the function.

4 System software simulation and testing

4.1 Software Simulation

The use of eda tools for the design of Quartus Ⅱ 6. O modulator software programming completed by compiler software simulation environment shown in Figure 4, in which the system clk clock oscillator, addr40 for the phase accumulator, a_in for A / D converter 8-bit output signal, fword for word frequency, fout output wave form of the modulation signal amplitude value.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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4.2 System Testing and Analysis

System testing through spectrum analyzer IFR2399A to complete hardware test. Figure 5 in the same hardware platform to achieve MSK modulation spectrum map, Figure 6 that the frequency spectrum GMSK modulation. Compare the two plans can be found, as a result of adding a Gaussian filter, GMSK spectrum more compact band attenuation also faster than MSK. At the same time by the test results can be seen as the carrier frequency 200 kHz, main lobe width and attenuation conditions in line with the theoretical results of the analysis.

Based on the FPGA and the GMSK modulator CMX589A Design and Implementation

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5 Conclusion

In this paper, the realization of a FPGA-based CMX589A and GMSK modulator. System uses a master-slave structure, MCUby GMSK modulator for the control of system parameters, CMX589A module base-band signal the completion of Gaussian filtering, FM modulator using direct digital frequency synthesis (DDS) in the FPGA hardware platform, the system maximum output frequency of 25 MHz. At the same time, the system has a very wide base-band signal data and modem control features such as flexible parameters, and the orthogonal modulation scheme to overcome the strict orthogonal carrier defects difficult. Test results show that the transfer has been a constant signal envelope, spectrum to meet the design requirements for CDPD, and other non-central station communication systems.


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